Hi
I need to know the relationship between the rising edge of CLK_OUT and the data from the SN65LVDS93 Serialzer. We are doing a design that uses this device feeding a Xilinx FPGA and we need this information to ensure we synchronise the incoming data stream correctly.
Figure 1 of the datasheet suggests we should wait 2 clock cycles from the rising edge of CLKOUT before we start a new cycle but there is no timing information given. The SN65LVDS93 usually interfaces to a SN74LVDS94 and this datasheet suggests the rising edge is coincident with the start of a cycle. Can someone please clarify this timing.
Thanks,
Mike
