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DS80PCIE800 EEPROM register description missing from datasheet

Richard Baum
Prodigy 140 points
Other Parts Discussed in Thread: DS80PCI810, DS80PCI800

I am working on a PCIE Gen 3 over cable design.  I am using a DS80PCIE800 part that is set to configure itself via EEPROM (SMBUS MASTER).  In table 6 of the datasheet there are a number of undocumented register bits.  Examples include rxdet_btb_en, RD_delay_sel, rx_delay_sel, chx_Sel_scp, chx_Sel_mode.  There are some others.  Is there another document that breaks down what some of these are used for?

Thank you,
Richard

  • 0
    TI__Mastermind 29655 points

    Hi Richard,

    These undocumented register bits in the EEPROM table are actually internal reserved functions and should not be changed from the default listing in their corresponding Register Map table for proper operation. We do not have documentation for these internal reserved functions that we can disclose, unfortunately.

    Thanks,

    Michael

  • 0 in reply to Michael Lu (Santa Clara)
    Prodigy 140 points
    It seems like some of the register bit names look similar to some that are documented but not exactly. I don't want to change something I should not. Is there a document that masks out all of the reserved bits?
  • 0 in reply to Richard Baum
    TI__Mastermind 29655 points

    Hi Richard,

    I made a more detailed table to ensure the appropriate bits are marked as Reserved. Please see the attached table.

    DS80PCI800 EEPROM Map Description.xlsx

    Thanks,

    Michael

  • 0 in reply to Michael Lu (Santa Clara)
    Prodigy 140 points
    Can you provide a similar spreadsheet for the DS80PCI810 part? We are having some difficulty getting PCIE Gen 3 working with a Mellanox target. All other Gen 3 targets seem to work fine. I want to make sure we are setting the EEPROM settings correctly. Thank you.
  • 0 in reply to Richard Baum
    TI__Mastermind 29655 points

    Hi Richard,

    This table is already included in the DS80PCI810 datasheet. Please see Table 6 for more information.

    Thanks,

    Michael

  • 0 in reply to Michael Lu (Santa Clara)
    Prodigy 140 points

    We see bits [6:5] in the SMB Slave mode register offset 0x11 change.  The datasheet says to set these to 0 but we see them come up as 00, 11 and 01 occasionally.  This seems to be correlated to the connection being successful at gen 3 vs gen 2 or 1.  Do you have any information on the function of these two bits.  Again, this is for a DS80PCIE810, not the 800.  We are trying to track down a problem with connecting to a Mellanox target over PCIE.  All other GEN 3 target endpoints seem to link without issue.  The Mellanox will not connect properly to the host through the 800 or 810 parts.  

    Thank you,

    Richard

  • 0 in reply to Richard Baum
    TI__Mastermind 29655 points
    Hi Richard,

    In the DS80PCI800, these bits reflect what the detected PCIe Gen rate is (00 = Gen1, 01 = Gen2, 11 = Gen3), assuming that the RATE pin is floating. These bits are observation bits only. When we were validating the DS80PCI810, we noticed some sporadic behavior for these bits, so though they may report the PCIe Gen rate for the majority of test cases, it is not guaranteed in production. Therefore, we elected to make these bits as reserved.

    In the DS80PCI800, the detected PCIe Gen Rate would determine whether the incoming signal goes through the repeater's limiting amplifier driver (Gen1, 2) or non-limiting/linear amplifier driver (Gen 3). In the DS80PCI810, there is no limiting amplifier option, so the detected PCIe Gen Rate does not affect how the signal is driven out of the repeater. The DS80PCI810 will always output signal through its linear amplifier, and the bits that are read back from Reg 0x11[6:5] do not indicate if the repeater is "fixing" the data rate to a specific PCIe Gen.

    To aid with your issue, do you have a schematic or register settings you can share? I wonder whether there is something that is causing our device not to interoperate well with this Mellanox target.

    Thanks,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    Prodigy 140 points

    Our setup involves a PLX (now Avago) 8796 PCIE Switch.  There are two 8 lane ports that go off board.  One port goes direct to a connector, one goes through the DS80PCI810 parts and then to a connector.  We have one DS80PCI810 part use all 8 repeaters for the 8 transmit lanes and one part for the 8 receive lanes.  We have tested a few other Gen3 devices in the connector with the DS80PCI810 parts and they all work ok but any time we connect a Mellanox device, it does not work at Gen3.  If we plug the Mellanox device in to the connector without the DS80PCI810 parts, it connects to the PLX switch at gen3 without issues.  It seems to be some incompatibility with the Mellanox and the DS80PCI810 parts.  We have tried adjusting all three settings (EQ, VOD and VOD_DB) in just about every combination we could and it does not seem to change the situation.

    I have attached the schematic and a text file that has the data from the EEPROM

    Fullscreen DS80PCI810_EEPROM.txt Download 
    4E 00 08 00 22 00 47 00
22 00 22 00 22 00 47 00
b6 00 dB 00 47 00 22 00
6c 00 91 00 22 00 22 00
22 00 00 00 06 47 02 00
AE 00 20 0A E0 02 00 AE
00 20 0A E0 01 84 01 5C
00 40 15 C0 04 01 5C 00
40 15 C0 00 00 54 54 00
00 06 47 02 00 AE 00 20
0A E0 02 00 AE 00 20 0A
E0 01 84 01 5C 00 40 15
C0 04 01 5C 00 40 15 C0
00 00 54 54 00 00 06 47
02 2C AE 00 22 CA E0 02
2C AE 00 22 CA E0 01 84
59 5C 00 45 95 C0 04 59
5C 00 45 95 C0 00 00 54
54 00 00 06 47 02 2C AE
00 22 CA E0 02 2C AE 00
22 CA E0 01 84 59 5C 00
45 95 C0 04 59 5C 00 45
95 C0 00 00 54 54 00 00
06 47 02 00 AB 00 20 0A
B0 02 00 AB 00 20 0A B0
09 84 01 56 00 40 15 60
04 01 56 00 40 15 60 00
00 54 54 00 00 06 47 02
00 AB 00 20 0A B0 02 00
AB 00 20 0A B0 09 84 01
56 00 40 15 60 04 01 56
00 40 15 60 00 00 54 54
    10GE_CONNECTOR.PDF