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SN65DP159 Timing Requirements

Timothy Starr
Expert 2445 points

Hello-

We're asking what the phase relationship between the high speed clock and data into the dp159 needs to be. The reason we ask is that we see no info in the dp159 datasheet regarding this.

We are using a Xilinx HDMI project (and again we seen no constraint for the Xilinx TMDS clock output relative to the Xilinx TMDS data output, thus the concern. 

Also will the sink of the HDMI signal (out of the DP159) require certain set up and hold times? If so could you let us know what they are?

Thanks and Best Regards,

-Tim Starr on behalf of JA@SS

  • 0
    TI__Mastermind 23815 points

    Hi Timothy,

    TMDS ckl and Data signals should be on phase.

    From specification:

    The T.M.D.S. clock channel carries a character-rate frequency reference from which the receiver produces a bit-rate sample clock for the incoming serial streams.Due to the high pair-to-pair skew that must be tolerated, the phase of the derived sample clock must be adjusted individually for each data channel.
    The T.M.D.S. receiver must determine the location of character boundaries in the serial data streams. Once character boundaries are established on all data channels, the receiver isdefined to be synchronized to the serial streams, and may recover T.M.D.S.characters fromthe data channels for decode. The T.M.D.S. data stream provides periodic cues for decoder/synchronization.

    No setup and hold times are required since TMDS CLK is a reference clk, inside receiver a PLL will regenerate sampling clock.

    This document contains information you can use as reference: http://www.xilinx.com/support/documentation/application_notes/xapp460.pdf

    Regards