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TLK10232_10G_Data_Error

user4366098
Prodigy 100 points
Other Parts Discussed in Thread: TLK10232

Hi，everyone！

now , i meet a problem , device application scenario is as follows :

FPGA(XAUI_10G) --> TLK10232(Low speed channel:4 lanes ) -->TLK10232(High speed channel) -->{ fiber loopback } TLK10232(High speed channel) -->TLK10232(Low speed channel:4 lanes)-->FPGA(XAUI_10G)  ;FPGA is the sender,and also is the receiver .

the tlk10232 works in "general purpose(10G) serdes mode",when synchronization between the FPGA and TLK10232, and four Lane word alignment . FPGA starts send some frames (frame length is 1600 bytes, the inter-frame gap is 40 bytes), after TLK10232 circle data loopback , FPGA sometimes receive a 1608 bytes frame, now , fpga xaui ip's state is ok , no error has occurred, and TLK10232's low_speed_error_counter  and high_speed_error_counter is zero ,problem where it occurs ? 

sorry, English is not good enough, a bit difficult to understand.

who can give some suggestions or ideas ?

thanks !!!

  • 0
    TI__Genius 16150 points

    Hi,

    Could you try enabling FEC (Forward Error Correction)?

    FEC option is able to correct a burst errors up to 11 bits. In the TX data path, the FEC logic resides between the scrambler and gearbox, on the other hand, in the RX datapath, FEC resides between the gearbox and descrambler. Frame alignment is handled inside the RX FEC block during FEC operation, and the RX gearbox sync header alignment is bypassed. This is due to latency is increased in both RX and TX data paths with FEC enable, it is disabled by default and must be enabled through MDIO programming (Is important to mention that FEC by nature will add latency due to frame storage).

    I hope this helps, please let me know if you have more queries or concerns.

    Best Regards!

    Luis Omar Morán Serna

    High Speed Interface

    SWAT Team

  • 0 in reply to Luis Omar Moran
    Prodigy 100 points

    Hi,

    Thank you for your suggestion!!!

    1 : tlk10232 can works in 10GBASE-KR MODE (this 10GBASE-KR MODE has FEC function, when the MODE_SEL pin is low , ST pin is low , and Register 1E.0001 bit 10 is 0), but now fpga's( xaui ip ) word alignment state indication signal is not ok .

    2:so i have to use the GENERAL PURPOSE (10G) SERDES MODE ( when the MODE_SEL pin is high , ST pin is low , and Register 1E.0001 bit 10 is 0), fpga's( xaui ip ) word alignment state indication signal is ok, this mode has no FEC function . but now it has some problems , when fpga continuously start sending some frame (frame size is 1600 bytes , every inter-frame gap is 200 bytes ),through tlk10232 loopback ,sometimes ,fpga receives a frame has 1612 bytes ,now fpga xaui ip's receiving and sending status indication is ok , and tlk10232's internal registers (HS_ERROR_COUNTER , LS_LN01/2/3_ERROR_COUNTER ) are all 0 .

    now i have two questions :

    1、why when tlk10232 works at 10GBASE-KR MODE, the fpga xaui ip's word alignment state indication signal is not ok(even tlk10232 is configurated at loopback mode) , when tlk10232 works at  GENERAL PURPOSE (10G) SERDES MODE, the fpga xaui ip's word alignment state indication signal is  ok.Is there any difference between 10GBASE-KR MODE and GENERAL PURPOSE (10G) SERDES MODE ;

    2、when i want to use this tlk10232 chip ,is there any caution ?!

  • 0 in reply to user4366098
    TI__Genius 16150 points

    Hello,

    There are several differences between 10G General Purpose & 10GBASE-KR, below you can see the block diagram of both modes:

    10GBASE-KR mode TLK10232 has built XAUI Lane Alignment, hence, if your application is:

    FPGA(XAUI) ==> TLK10232(LS Channel:4 lanes ) ==>TLK10232(HS) ==>[Fiber Loopback] TLK10232(HS) ==>TLK10232(LS Channel:4 lanes) ==>FPGA(XAUI_10G)  [FPGA is the sender,and also is the receiver]

    Could you clarify me why are you using the General Purpose mode instead 10GBASE-KR?

    Because, in the 10GBASE-KR mode, the TLK10232 performs serialization of the 8B/10B encoded XAUI data stream presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs in 64B/66B encoding format. Likewise, the TLK10232 performs deserialization of 64B/66B encoded data streams presented on its high speed side data inputs. The deserialized 64B/66B data is presented in XAUI 8B/10B format on the low speed side outputs. Link Training is supported in this mode as well as Forward Error Correction (FEC) for extended length applications.

    On the other hand in the General Purpose SERDES mode, the TLK10232 performs 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side outputs. Likewise, the TLK10232 performs 1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high speed side data inputs. The deserialized 8B/10B encoded data is presented on the low speed side outputs. Depending on the serialization/deserialization ratio, the low speed side data rate can range from 0.5 Gbps to 5 Gbps and the high speed side data rate can range from 1 Gbps to 10 Gbps. 1:1 retime mode is also supported but limited to 1 Gbps to 5 Gbps rates.

    I hope this helps.

    Best Regards!

    Luis Omar Morán Serna

    High Speed Interface

    SWAT Team

  • 0 in reply to Luis Omar Moran
    Prodigy 100 points

    Hi:

    First , thank you for your suggestion.

    my application is:

    FPGA(XAUI) ==> TLK10232(LS Channel:4 lanes ) ==>TLK10232(HS) ==>[Fiber Loopback] TLK10232(HS) ==>TLK10232(LS Channel:4 lanes) ==>FPGA(XAUI_10G)  [FPGA is the sender,and also is the receiver].

    1.when i use TLK10232 10GBASE-KR mode , the FPGA XAUI ip‘s every lane is not at synchronization status , and so the word alignment is not ok , even i configure the tlk10232 loopback (through MDIO interface,1E.000B register is configured 16'h0D11  ),so i suspect the tlk10232 can not work at 10GBASE-KR mode ;

    2.now when i use TLK10232 10G General Purpose mode , the FPGA XAUI ip‘s every lane is at  synchronization status , and the word alignment is ok ;

    so, i have to use TLK10232 10G General Purpose mode .

    Is there some registers have to configure before use the tlk10232 , if i want to use it  10GBASE-KR mode ? 

    thank you !!!

    Best Regards!

  • 0 in reply to user4366098
    TI__Genius 16150 points

    Hi,

    Attached you will find a document that specifies the procedure to use different modes of 10GBASE-KR.1004.tlk10232_BringupProcedures_v2.pdf

    I hope this helps!

    Best Regards!

    Luis Omar Morán Serna

    High Speed Interface Group

    SWAT Team

  • 0 in reply to Luis Omar Moran
    Prodigy 100 points

    Hi,

    Thank you , when i configure the tlk10232 using "KR using manual mode settings learned from LinkTraining", the fpga xaui ip is ok , its 

    word alignment Instruction is ok , and now when the fpga sends frames , through tlk10232 loopback , the received data is ok .

    thank you !!!

    Best Regards!