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DS90C187 / Question about Data Enable signal

S.Satoshi
Guru 21675 points

Hi Everyone,

Let me ask about Data Enable signal as below.

  • Please let me know about timing requirement from DE rising edge to INA/Bn and IN_CLK (see attached)
  • Can the signal that is synchronous with Horizontal Sync signal use as DE signal ?
  • Can DE pin be pulled up externally and input IN_CLK and INA_B at DE is already High ?

Best Regards,

Sonoki / Japan Disty

  • 0
    TI__Guru* 93670 points
    Hi Satoshi-San,

    1). This is a synchronous system and LVCMOS input signals are sampled or synchronized using IN_CLK . Please note figure 7 of the data sheet for these timings.
    2). The answer is no. We cannot use a signal that is synchronous to the HSYNC since there could be some video frames that may have odd number of lines.
    3). The answer is no. Rising edge of DE indicates odd frame and we cannot tie this signal high.

    Regards,,nasser
  • 0 in reply to Nasser Mohammadi
    Guru 21675 points

    Hi Nasser-san,

    Thank you for your response. Let me ask more about DE signal.

    #4,

    In your answer for #2 in previous post, you commented that the signal that is synchronous to the HSYNC can not use for DE signal. Then can the signal that is kept Low at back port and front porch be used? Please see attached.

    #5,

    Please let me know the requirement about DE signal. For example when it should be turned from High to Low.

    #6,

    In your comment for #3, you commented that rising edge of DE indicates odd frame. Then can we care about odd frame when they use progressive, not interlace? Please let me know the relationship more about  odd frame and DE signal.

    Best Regards,

    Sonoki

  • 0 in reply to S.Satoshi
    Guru 21675 points

    Attached for #4.

  • 0 in reply to S.Satoshi
    TI__Guru* 93670 points

    Hi Satoshi-San,

    1). Please refer to the data sheet figure 7 for the setup and hold time for DE signal.

    2). I have attached two diagrams showing DE timing and also LVDS output in single pixel in and dual pixel out. DE stays high during the red mark you have shown above.

    Regards,,nasser