• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 33 subscribers
  • Views 669 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS99R105-6 / waveform quality of clock

K.Yaita
Guru 29720 points

Other Parts Discussed in Thread: DS99R105

Hi Team

My customer considers to use DS99R105/6(Serdes).

Is there any concern to transmit 10MHz clock in terms of waveform quality? 
He concerns if it could maintain original clock duty and frequency.

The datasheet features shows "3 MHz–40 MHz Clock Embedded", so I believe it is no problem.

Best Regards,
Yaita

  • 0
    TI__Guru* 93570 points
    Kensuke-San,

    DS99R105 is one of our Channel Link 2 family of products. By clock embedded we mean the clock is embedded on the serial differential signal(DOUT= and DOUT-). As you indicated the pixel clock(TCLK) could be between 3 and 40 MHz. Please make sure there is no overshoot, undershoot, or ringing on the TCLK or data lines.

    Regards,,nasser
  • 0 in reply to Nasser Mohammadi
    Guru 29720 points

    Hi Nasser-san,

    Thank you for your reply. I understood.

    How about the data transmission?
    Could it maintain original(input) duty and frequency through serdes transmission?
    (For example, is it possible case that outputs have additional jitter through transmission?)

    Best Regards
    Yaita

  • 0 in reply to K.Yaita
    TI__Guru* 93570 points

    Kensuke-San,

    Normally the majority of the jitter is coming from the incoming data or input clock jitter. The device may have some residual jitter but it is far less than the incoming data jitter. The residual jitter could be in order of 10 mUI. For example at 40MHz TCLK, data rate is about 1.12 Gbps. 1 UI is about 890 pS. 10 mUI is about 8.9 pS.

    These devices maintain original duty cycle and frequency the data pattern. Please note TCLK and setup and hold time should be within the device requirements/specifications as noted in figure 6 of the data sheet.

     Regards,,nasser