Refer to the XIO2001 datasheet PDF page 116:
All synchronous PCI bus signals must be length matched to meet clock setup and hold requirements.
However, in the PDF page 123
There is no matching requirement on the length of the Address/Data signals with respect to Clock Signal, though,
there is a limitation on the maximum length of the Address/Data signal length depending upon the PCI Bus
speed. The length matching of clock signals in PCI bus is not very critical. It is however, often, not too difficult to
match it within 100 mils. The PCI Clock Signals should be slightly longer than the longest trace on the PCI bus.
When 100 mil recommendations become impractical due to board space constraints, this can be relaxed up to a
recommended maximum of 250 mils.
I am wondering IF there's any length match requirement for the PCI Bus Signals because in the datasheet there are mentioned on the length match.
IF there is a length match requirement, what is the required length match distance ?
Thank you!
Chun Ling Chen
