PCI2060 primary and secondary bus clocks

Daisuke Maeda

Guru 20215 points

When using the SEC_ASYNC_CLK as the clock input to generate the secondary bus clocks:

Can the each of primary and secondary bus clocks be any frequency to be not synchronized to each other? For example, P_CLK is 66MHz then S_CLK is 15.625MHz. The combinations of 25MHz, 33MHz, 50MHz and 66MHz are described in the datasheet.

Are there the timing requirements of the relationship between the primary and secondary bus clocks? Only the relationship between P_CLK and S_CLK in the 66MHz clocks is described in the datasheet.

Best regards,

Daisuke

over 10 years ago

0 Elias Villegas M. over 10 years ago

TI__Guru* 76130 points

Hello,
The secondary clock can never be faster than the primary clock, this is a limitation by the PCI Spec.
When SEC_ASYNC_SEL is high then you have to provide a clock for the secondary bus, theoretically it could be any frequency supported by the PCI spec, however I recommend using one of the frequencies described on Table 3-11 in Datasheet.

There are no timing requirements for P_CLK and a asynchronous secondary clock, the only requirement is to connect the asynchronous clock to SEC_ASYNC_CLK.
Regards

0 Daisuke Maeda over 10 years ago in reply to Elias Villegas M.

Guru 20215 points

Hi Elias,

Thank you for your reply.

Can the secondary clock never be faster than the primary clock? The datasheet describes: "The PCI2060 bridge is capable of supporting operations in which the secondary bus clock frequencies can be greater than the primary clock frequency.", and that seems to be possible in Table 3-11.

Best regards,

Daisuke

0 Elias Villegas M. over 10 years ago in reply to Daisuke Maeda

TI__Guru* 76130 points

Correct,
When using an external clock as the secondary it can be greater than the primary clock.
Regards

0 Daisuke Maeda over 10 years ago in reply to Elias Villegas M.

Guru 20215 points

Hi Elias,

Thank you for your reply.

Best regards,

Daisuke

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PCI2060 primary and secondary bus clocks