My customer has a new design using TI DS25CP102. The input IN_0 is PCIE gen 1. IN_1 is one of the XAUI lane.
The initial testing of the signal P4080_PST is low. However, the input IN_0P and output OUT_1P are different.
Q1: Does this chip support PCIE signaling?
Q2: Please review the connections and do you see any mistake?
Q3: What is the possible reason why OUT_1P is differnet than IN_0P?
please advise.