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TLK1521 sync pattern

Haim Cohen
Prodigy 40 points


1. if a sync pattern is received, is the sync pattern output on the parallel data pins? how can the receiver side distinguish between sync pattern and data words?

2. if the sync pattern is output on the parallel interface, what is the order of the bits in the sync pattern of the TLK1521? is the '1' at the lower bits and '0' on the higher bits, or the other way around?

  • 0
    TI__Genius 16150 points
    Hi Haim,

    The 18 bit parallel data is encoded into 20 bits by framing the 18-bit data with a START and a STOP bit. On the other hand, TLK1521 is able to to send specific SYNC patterns (9 ones & 9 zeros) switching at the input clock rate.

    When the deserializer detects edge transitions at the serial input, it attempts to lock to the embedded clock information. The deserializer LOCKB output remains inactive while its clock/data recovery (CDR) locks to the incoming data or SYNC patterns present on the serial input. When the deserializer locks to the serial data, the LOCKB output goes active. When LOCKB is active, the deserializer outputs represent incoming serial data. One approach is to tie the deserializer LOCKB output directly to the SYNC input of the transmitter. This assures that enough SYNC patterns are sent to achieve deserializer lock.


    Best Regards!
    Luis Omar Morán Serna
    High Speed Interface
    SWAT Team