Hi,
We are using sn65dsi83 bridge chip with our application processor to convert 4 lane mipi dsi signals to 4 lane LVDS signals. We are using Hantronics' 10" LVDS panel.
LVDS panel information:
4 data lane + 1 clock lane
Pixel clock - 71.1 MHz
Horizontal Active - 1280
Vertical Active - 800
BPP - 24
Horizontal pulse width - 80
Horizontal front porch - 40
Horizontal back porch - 40
Vertical pulse width - 9
Vertical front porch - 7
Vertical back porch - 7
DSI information:
4 data lane + 1 clock lane
DSI Clock frequency 427MHz
We have performed following experiments to test bridge chip with our application processor,
1. Generated fixed pattern from bridge chip using external reference clock as source clock. We are able to see pattern on panel with above video parameter. Refer attach configuration file
i2cset -f -y 0 0x2d 0x20 0x00 i2cset -f -y 0 0x2d 0x21 0x05 i2cset -f -y 0 0x2d 0x24 0x20 i2cset -f -y 0 0x2d 0x25 0x03 i2cset -f -y 0 0x2d 0x2c 0x50 i2cset -f -y 0 0x2d 0x2d 0x00 i2cset -f -y 0 0x2d 0x30 0x09 i2cset -f -y 0 0x2d 0x31 0x00 i2cset -f -y 0 0x2d 0x34 0x28 i2cset -f -y 0 0x2d 0x36 0x07 i2cset -f -y 0 0x2d 0x38 0x28 i2cset -f -y 0 0x2d 0x3a 0x07 i2cset -f -y 0 0x2d 0x3c 0x10 i2cset -f -y 0 0x2d 0x0a 0x04 i2cset -f -y 0 0x2d 0x0b 0x02 i2cset -f -y 0 0x2d 0x10 0x00 i2cset -f -y 0 0x2d 0x18 0x78 sleep 1 i2cset -f -y 0 0x2d 0x0d 0x01
2. Generated fixed pattern from bridge chip using DSI clock frequency coming from application processor as source clock. We are able to see pattern on panel with above video parameter. Refer attach configuration file
i2cset -f -y 0 0x2d 0x20 0x00 i2cset -f -y 0 0x2d 0x21 0x05 i2cset -f -y 0 0x2d 0x24 0x20 i2cset -f -y 0 0x2d 0x25 0x03 i2cset -f -y 0 0x2d 0x2c 0x50 i2cset -f -y 0 0x2d 0x2d 0x00 i2cset -f -y 0 0x2d 0x30 0x09 i2cset -f -y 0 0x2d 0x31 0x00 i2cset -f -y 0 0x2d 0x34 0x28 i2cset -f -y 0 0x2d 0x36 0x07 i2cset -f -y 0 0x2d 0x38 0x28 i2cset -f -y 0 0x2d 0x3a 0x07 i2cset -f -y 0 0x2d 0x3c 0x10 i2cset -f -y 0 0x2d 0x0a 0x05 i2cset -f -y 0 0x2d 0x0b 0x10 i2cset -f -y 0 0x2d 0x10 0x00 i2cset -f -y 0 0x2d 0x12 0x56 i2cset -f -y 0 0x2d 0x18 0x78 sleep 1 i2cset -f -y 0 0x2d 0x0d 0x01
3. Now we are trying to display live data on LVDS panel by converting 4 lane dsi data coming from processor with DSI clock frequency coming from processor as source clock. But we are not able to see anything on panel. We have probed on DSI clock and 4 lane DSI data which is coming on to the input of the bridge chip. We also observed that bridge chip is able to produced required output LVDS clock 71.1 MHz but not data. There is no data coming on output of the bridge chip. Please refer attach configuration file
i2cset -f -y 0 0x2d 0x20 0x00 i2cset -f -y 0 0x2d 0x21 0x05 i2cset -f -y 0 0x2d 0x24 0x20 i2cset -f -y 0 0x2d 0x25 0x03 i2cset -f -y 0 0x2d 0x28 0x20 i2cset -f -y 0 0x2d 0x29 0x00 i2cset -f -y 0 0x2d 0x2c 0x50 i2cset -f -y 0 0x2d 0x2d 0x00 i2cset -f -y 0 0x2d 0x30 0x09 i2cset -f -y 0 0x2d 0x31 0x00 i2cset -f -y 0 0x2d 0x34 0x28 i2cset -f -y 0 0x2d 0x36 0x07 i2cset -f -y 0 0x2d 0x38 0x28 i2cset -f -y 0 0x2d 0x3a 0x07 i2cset -f -y 0 0x2d 0x0a 0x05 i2cset -f -y 0 0x2d 0x0b 0x10 i2cset -f -y 0 0x2d 0x10 0x26 i2cset -f -y 0 0x2d 0x12 0x56 i2cset -f -y 0 0x2d 0x18 0x78 sleep 1 i2cset -f -y 0 0x2d 0x0d 0x01
Is there any configuration we are missing in third experiment ? Please provide some input so that we can look into proper direction.
Thanks and Regards,
Shabbir Limdiwala
