We need to implement a function that requires cascading two HD3SS3412 devices for a PCIE application where the TX lanes are AC coupled (standard PCIE implementations). Is there any biasing required between the two cascaded device?
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We need to implement a function that requires cascading two HD3SS3412 devices for a PCIE application where the TX lanes are AC coupled (standard PCIE implementations). Is there any biasing required between the two cascaded device?
Hello,
The HD3SS3412 requires bias voltage, typically this biasing is provided either by the host or the endpoint, if the available bias voltage is higher than 2V then you have to provide a controlled bias voltage lower than 2V.
The location of the AC coupling caps is also relevant for the biasing.
Please see the attached app note.
Regards.