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Many SN65LVDS93A-Q1 Application Questions

Anthony Ward
Prodigy 110 points
Other Parts Discussed in Thread: SN65LVDS93A-Q1

I have many questions about application of the SN65LVDS93A-Q1. Thank you in advance for answering them.

(1) In the schematic example in the SN65LVDS93A-Q1 datasheet, the data inputs all have external 4.7k ohm pullup resistors. Is 4.7k ohm pullup on data inputs recommended for application?

(2) For our data inputs that we are tying only what value resistors should we use to tie them to the rail?

(3) Can we tie GND pins directly to the ground plane, or do we need a resistor or something inbetween GND pin and ground?

(4) Figures 15, 16, and 17 show PLLVCC and LVDSVCC tied together, while figure 13 shows PLLVCC, LVDSVCC, and VCC tied together. Is it recommended to tie PLLVCC, LVDSVCC, and VCC together, and use the same decoupling caps? If not, is it recommended to tie PLVCC and LVDSVCC together, and use the same decoupling caps?

(6) If our IOVCC is going to be 3.3V, can we tie VCC, PLLVCC, LVDSVCC, and IOVCC all together, and use the same decoupling caps?

(5) What is the purpose of having a .1 uF and .01 uF caps in parallel for power pins? Why not just one .11 uF cap?

(6) If our IOVCC is going to be 3.3V, can we tie VCC, PLLVCC, LVDSVCC, and IOVCC all together?

(7) The DS90UR905Q needs series decoupling caps for its output LVDS lines. Do the LVDS output lines for the SN65LVDS93A-Q1 need series decoupling caps?

(8) Should the input pixel clock have a 50% duty cycle? we will want the output pixal clock to have 4/7 duty cycle. Will the serializer make the change from 50% to 4/7 duty cycle by itself?

 

Thanks again

  • 0
    Prodigy 110 points
    For question (1), I do not think that a 4.7k pullup is recommended, because the I/O description of input pins is "CMOS IN with pulldn". What value pulldown resistor is recommended?
    Also, if I have input pins that I want to tie deirectly to ground or Vccio, what value pullup/down resistor is recommended?
    Thanks
  • 0 in reply to Anthony Ward
    TI__Mastermind 36085 points
    Hello Anthony,

    I will review your questions and reply soon, also I am moving your post to the appropriate forum.

    Best regards,
    Diego.
  • 0 in reply to Diego Cortes
    Prodigy 110 points
    Thanks. For (2) I meant to say "For our data inputs that we are tying only TO THE RAIL, what value resistors should we use to tie them to the rail?"
  • 0
    TI__Mastermind 36085 points
    Hello Anthony,

    Here you go the feedback to your questions, please feel free to comment.

    1) The pull up resistors are optional, our EVM has these resistors for debugging purposes only.

    2) If you need the pull up resistors, then the 4.7KOhm is fine.

    3) You must connect the pins directly the GND terminals to ground.

    4) all the VCC pins can be connected together, it is the customer's decision to use multiple power supplies. For the decoupling caps, we recommend to use the configuration in the figure 14, regardless you have single or multiple power rails.

    5) for stability purposes

    6) Yes you can, however we recommend to use the number of capacitors in figure 14.

    7) It is not necessary to have the decoupling caps on the outputs, this depends on the receiver input characteristics.

    8) The duty cycle of the input clock must be between 40% and 60%.

    Best regards,
    Diego.
  • 0 in reply to Diego Cortes
    Prodigy 110 points
    Thanks for the response.
    Can you elaborate more on (5)? I do not want to use two capacitors if I can use only one
  • 0 in reply to Anthony Ward
    TI__Mastermind 36085 points
    Hello,

    All the capacitors have a parasitic inductance, therefore is not the same to have only one capacitor. This parallel array has a better performance @ lower frequencies in comparison with the single cap scheme.

    Regards,
    Diego.