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Does DS90UB913Q actually work with 10MHz CLK? Does it work with 2.8V on VDDIO?

Vivek Sikri
Intellectual 300 points

Hello,

Having some trouble with the DS90UB913Q/914Q chipset and I'm hoping someone can help me please.

I have used this chipset successfully on another design. In my new design I need to run the PCLK very slow, less than 20MHz and ideally 12.5MHz. According to the DS90UB913Q spec it should work all the way down to 10MHz. This isn't true of the DS90UB913A which is spec'd down to 25MHz.

Both of these scenarios are using 12 bit LF mode so 1:1 ratio between CLKIN and PCLK.

Scenario 1:
External clock mode with GPO3/CLKIN receiving a 25MHz. GPO2 puts out 12.5MHz as expected. I have PCLK coming in at 25MHz. In this scenario the chipset locks fine.

Scenario 2:
When I change GPO3/CLKIN and PCLK to 12.5MHz the system no longer locks. No other changes. Strange!

Separately but possibly related when I run VDDIO at 1.8V the scenario 1 above locks. If I change VDDIO to 2.8V then I no longer get a lock signal. This despite the fact that I'm changing ONLY VDDIO (and PDB pullup to it). The Mode pin is pulled to 1.8V as per datasheet. Signals coming into the Deserializer also change between 1.8V and 2.8V as they are all off the same voltage supply.

Please help! I have a customer demo next week.

Thanks,

Vivek

  • 0
    TI__Expert 5210 points
    Hello Vivek,

    Have you tried sourcing the PCLK to the 913Q in imager mode (i.e. NOT external clock mode)? Does it still LOCK @ 12.5 MHz? Also, do you have EVM's on hand where you could try swapping a 913Q EVM for your serializer board and seeing if you can reproduce the issue? The same goes for swapping the 914Q EVM with your deserializer board.

    To see what pins are being sourced by VDDIO on the serializer side, I would most likely need to see the schematic to understand why you're see why there might be a system dependency on VDDIO.

    -Sean