Hi team
We confirmed Link_up following "Implementing_a_CLHS_Interface_Using_the_TLK3134.pdf".
After that We checked OverFlow. and TX_WIDE_FIFO_Overflow is occurred.
Error condition of TX_WIDE_FIFO_Overflow is shown by "Implementing_a_CLHS_Interface_Using_the_TLK3134.pdf" as follows,
These bits indicate overflow or underflow conditions in the transmit- or receive-direction FIFOs.
When FIFO collisions are detected, it means that there is some mismatch between the rate to
which the FIFO is written and the rate at which it is read. If FIFO collisions are detected, the
clocking architecture chosen and the quality of the reference clock should be examined.
Could you advise the way to check cause of such error by clock quality?
Regards,
Yoshihiro