• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 33 subscribers
  • Views 853 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMH1983 - Lock step size setting

Kawai
Guru 19785 points
Other Parts Discussed in Thread: LMH1983

Hello Team,

Please teach me about the lock indication condition.

I am understanding that "Lock Threshold" and "Lock step size" is the requirement  to show UNLOCK status = Low.

For "Lock step size", what is the time difference for each step ? i believe it is few ns or something like that.

Best Regards,

Kawai

  • 0
    Guru 19785 points
    Hello Team,

    Could you also teach me what is the symbol for "LOCK TRESHOLD" and what each step size is ?

    Best Regards,
    Kawai
  • 0 in reply to Kawai
    TI__Guru* 93670 points
    Hi Kawai-San,

    When the CLOCK1 PLL is in a LOCK condition, the VCXO frequency (or a multiple of it) is exactly the same as the reference frequency. If the reference frequency has no jitter or wander on it, and the VCXO does not drift, then the system will continue to run with no adjustment made to the control line on the VCXO. If there is jitter on the reference, then the PLL will supply positive and negative pulses to the loop filter, to try to keep the VCXO tracking the reference. If the PLL is out of lock, then the PLL will be generating many pulses to try and drive the VCXO to the proper frequency. The lock detect circuit in the LMH1983 declares NOLOCK if the number of pulses sent out in a specified period exceeds a certain threshold. The LOCK_STEP_SIZE register specifies the period of time over which the LMH1983 counts pulses, and is measured in terms of Hsync pulses, the LOCK_THRESHOLD register specifies the maximum number of pulses that can be expected within this period and have the device still considered to be in LOCK.

    Regards,,nasser
  • 0 in reply to Nasser Mohammadi
    Guru 19785 points
    Hello Nasser-san,

    Thank you for the explanation. I would like to know the window difference for each step size for each bit information.

    For example, default value for Lock Step Size is 5'b10000. When this changed to 5'b10001, what is the difference in time (window) between these two value ? I believe it is something like 1, 2, or 3 ns (TYP) for each step(bit).


    In addition to the Lock Step Size, how about "Lock Threshold" ?
    Would the symbol be ppm or % ? What is the step size for each bit increment/decrement ?

    Best Regards,
    Kawai
  • 0 in reply to Kawai
    TI__Guru* 93670 points
    Hi Kawai-San,

    The lock step size sets up a current reference for the internal circuit. This current reference is directly proportional to the step size. So the smaller the step size the higher the current reference which enables us to tolerate more jitter( without declaring loss of lock). Please note this parameter has not been characterized. I can check with the designer when he comes back from vacation on this so he can provide an estimate.

    Lock threshold specifies the maximum number of pulses that VCO generates over a period of time, about 9 Hsync pulses, and still be considered as lock condition. So we use the same time window, ~ 9 HSYNC pulses, to determine whether we are in lock or not.

    Regards,,nasser