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SN65LVDS104 3.3v Interfacing with 2.5v LVDS driver

rmaw
Prodigy 85 points

Hello,

I am interfacing this IC with an FPGA which has 2.5v on the IO bank that is driving the LVDS. All of the Vcm and differential voltages are within spec of each other, so I understand that the LVDS driver on the FPGA will work with this IC.

However I am wondering if there will be any problems with the 300k 3.3v pullup 'failsafe' circuit on this IC. The 3.3v is within spec of the FPGA pins, which have an absolute maximum IO voltage of 3.6 volts. But I am wondering if the 3.3v pullups might cause issue when the LVDS driver is switched on at configuration time. There will be 3.3v at the pins of the FPGA momentarily, before the driver has driven its Vcm.

Thanks for any help.

  • 0
    TI__Mastermind 36085 points
    Hello,

    You can check the maximum input current of the FPGA pins. take the worst case which would be to have the FPGA terminal driven to 0. therefore you will have a path from 3.3V to GND (FPGA pin) thru 300KOhms, which is about 11uA. If this value is within the spec then you should be fine.

    Regards,
    Diego