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TFP410 differential clock termination?

Tomoyuki Tanaka
Prodigy 10 points
Other Parts Discussed in Thread: TFP410

We are trying to use TFP410 with a differential clock input mode in the low signal swing mode (Vref=0.9V) . FPGA drives 148.5MHz clock for TFP410.

This question is similar to the following topic:

http://e2e.ti.com/support/interface/digital_interface/f/130/t/169607

What type of termination is required for IDCK+ and IDCK- signals in the differential clock input mode?

Please clarify / let me know its termination specification and IO interface standard for IDCK+/IDCK- for example SSTL, LVDS or etc.,

Regards,