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DS90UB913A-CXEVM with DS90UB914A design

Ben Missele
Prodigy 220 points
Other Parts Discussed in Thread: DS90UB913A-CXEVM

I have a board design using the DS90UB914A and providing power over coax. I have connected this board to the DS90UB913A-CXEVM and I see the PCLK on my DS90UB914A as a solid 50Mhz. I do not see the LOCK signal go high. There is no data being sent over the link between the boards as I have no camera source for the DS90UB913A-CXEVM. I also do not have I2C access to either part. I am using pull-ups and pull-down resistors on the DS90UB914A to set the modes. 

1) If there is no data present over the link, should I still expect to see the LOCK pin go high on the DS90UB914A? As said above, I do see the PCLK output of 50Mhz. 

2) I have set the DS90UB914A to BIST mode by tying the BIST pin high. I then set GPIO0 HIGH and GPIO1 LOW for a 25Mhz PCLK. From the datasheet, I would need I2C access to the DS90UB913A-CXEVM to place it into BIST mode, correct? It will not go into BIST mode automatically even if the DS90UB914A is sending BIST data, correct? When set in this mode, I do see the GPO LEDs on the DS90UB913A-CXEVM reflect the status of the GPIO pins. The PCLK output of the DS90UB914A is still 50Mhz in this mode. 

My goal is to verify that my new hardware is working and linking correctly to the serializer chip. 

Thanks for your help,

 Ben Missele

  • 0
    TI__Expert 5210 points
    Hello Ben,

    That is very weird that you are seeing a solid PCLK signal @ 50 MHz and a LOCK pin that is low. Technically, this is impossible because the clock-data recovery PLL inside of the 914A recovers both the clock signal and data from FPD-Link serial stream that is sent from the 913A. If the signal does not have good integrity (i.e. high jitter) the PLL can't recover it and LOCK won't go HIGH (meaning that you also won't see PCLK signal on LVCMOS 914A output either). Are you sure that you have set the correct scope settings to probe on LOCK?

    Also, what is preventing you from I2C access? The 913A EVM had I2C headers (SCL, SDA, VDD, and GND) for you to plug in an I2C master and connect either locally to the 913A or remotely to the 914A as shown here in this app note: www.ti.com/.../snla222.pdf


    1). Yes, LOCK will still go HIGH even in the absence of "true" data. The LVCMOS inputs on the 913A EVM are tied LOW with pulldowns mimicking an all 0's input pattern. ~50 MHz is the default PCLK in 10-bit mode which is internally generated inside the 913A in the absence of an externally supplied PCLK.

    2). No, I2C access is not required. BIST mode can be set on the deserializer only and any required control data to put the 913A in BIST mode will be sent automatically over the back channel. Taken from section 8.4.6 from the datasheet (www.ti.com/.../ds90ub913a-q1.pdf): In BIST DS90UB913A register 0x14[2:1] is automatically loaded from the DS90UB914A through the bi-directional control channel.

    Please see page 30 - 32 of the datasheet (specifically, section 8.4.8) for configuring BIST mode.

    -Sean