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LMH1981 SD Sync amplitudes

JohnW
Prodigy 150 points

Hello,

I am having some issues when interfacing to a camera PAL video signal where the first 5 sync amplitudes at the start of each field are about 40mV higher than subsequent syncs.

I note that the Electrical Characteristics table, on page 3 of the data sheet, specifies a maximum VIN-SYNC amplitude of 0.6V but I am interested in the note 6 that refers to this value, where the note states that the maximum difference between consecutive syncs should be less than 25mV. I suspect this is why I am having trouble interfacing to this video signal.

Could you please explain why this parameter of <25mV is important ,and what potential errors may occur when consecutive syncs exceed this value.

thank you

John 

  • 0
    TI__Mastermind 32575 points

    The different sync tip amplitudes could cause improper sync-tip clamping of the AC coupled input signal, and this may lead to problems with loss of sync.

    I suggest trying to debug/work-around by using a smaller input coupling cap value and/or adding a weak pull-down resistor between the coupling cap and Vin pin.  This would intentionally introduce some voltage droop to allow the sync-tip clamp circuit to conduct on each input sync pulse.  I suggest to try smaller input cap values first (0.01uF or 0.001uF), and see if that helps to avoid the sync loss.  If not, then try adding some pull-down resistor on Vin (100k or so?, or even loading it with a a high-impedance oscilloscope probe) and see if that helps.  

    Regards,
    Alan

  • 0 in reply to Alan O
    Prodigy 150 points

    Alan,

    thank you for your suggestion.

    Changing the capacitor value to 1nF without the use of the resistor has cured the problem with the camera sync amplitudes, although I have made some further tests as described:.

    I constructed a simple test circuit which allowed me to adjust the gain and offset of the video signal, and also added a further offset circuit that applied an offset only within the period where the sync amplitudes were causing a problem. This has allowed me to optimise the selection of the capacitor and resistor.

    I found that the optimum solution was using 10nF and 100k resistor, which allowed the sync amplitudes to differ by up to 100mV before the sync detection was corrupted. The 100mV offset would be much higher that I would ever expect in a real world situation, so I have decided to use these values which should prevent the issue of poor sync detection in applications of my circuit.

    Can you see disadvantages by using these values i.e. reduced sync detection jitter performance etc?

    regards

    John

  • 0 in reply to JohnW
    TI__Mastermind 32575 points

    Yes, higher output jitter is the drawback of introducing additional droop to negate the sync offset.

    Alan