• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 33 subscribers
  • Views 687 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PCLK Input Jitter Tolerance for ds90ub925q-q1

ttd
Mastermind 9005 points

Other Parts Discussed in Thread: DS90UB925Q-Q1

I have two questions about DS90UB925Q.

Datasheet(SNLS407D) describes following jitter Tolerance for PCLK.

tIJIT: PCLK Input Jitter Tolerance

Min:0.4UI, Typ:0.6UI

1.) Is following correct calcuration for tIJIT?

1UI=1/(35*65MHz)=0.44ns

0.4UI=0.176ns(Min for tIJIT)

2.) My understanding, more smaller jitter is better, so I think that datasheet should show max for worst case.

What is the reason that dataseet dosen't show max?

■datasheet

http://www.tij.co.jp/jp/lit/ds/symlink/ds90ub925q-q1.pdf

Best Regards, y.i

  • 0
    TI__Genius 13475 points
    Your calculations are correct. The jitter tolerance is the maximum amount of jitter that the device can take and still be able to maintain a link with the receiver. Because of this, for jitter tolerance, a larger number is better since the device will still be able to operate even with a larger amount of jitter on the clock.
    The actual jitter is also limited in frequency - if the jitter is very low frequency (<PCLK/40) then both the serializer and deserializer will be able to track the variations in the clock. If the jitter is very high frequency (>PCLK/20) then the serializer will be able to reject the jitter before it gets to the FPD link, so again, the device is relatively insensitive. The jitter that is in this middle frequency is the jitter which will make it harder for the link to be maintained.