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TPS65982 / HD3SS460 GPIO control

Other Parts Discussed in Thread: HD3SS460, TPS65982

My customer designed circuit with HD3SS460. Is pin assignment for operating HD3SS460 right for your FW?
   AMSEL -> GPIO0(B2)
   EN -> GPIO3(G11)
   POL -> Debug2(K2)

BTW, HD3SS460 needs tri-state for AMSEL, EN.
What external circuit of GPIO of TPS65982 do you recommend for middle mode? (e.g, pull-up or pull-dpwn?  What is resistor value?)

  • Saito-san,

    You can use any GPIO except GPIO4, 5, 9, 10, and 11 for HD3SS460 Mux.

    The web-based Config Tool will let you map the AMSEL, EN, and POL events to any GPIO.

    GPIO0, GPIO3, and DEBUG2 (GPIO14) will work.

    HD3SS460 requires tri-state for AMSEL. External circuitry would require a weak pull-up and pull-down to achieve a mid-rail voltage.

    So far, I have not heard of an application that requires tri-state for EN. If your customer needs this feature, please explain why it is needed in the application.

  • Thank you for your information. The customer downloaded your config tool and understood they can easily change pin assignmemt as any supported pins.
    I received an additional question from the customer.About EN:
    In the datasheet of HD3SS460(REVISED MARCH 2015), page4, it explains the pin type of EN is "3-level Input".
    And, in 8.4.1, page10, it shows middle mode of EN. Could you confirm the true application?
    RegardsSaito
  • HD3SS460 is a highly configurable crosspoint switch that can be used in many applications including Type-C Alt mode.
    The configurations with (POL = H/L, AMSEL =H/L, EN = H/L) are used to cover DP Alt mode pin assignment C through E on the DFP_D side, C and D on the UFP_D side. Other cases with AMSEL=M and EN=M are configurations that can be used for any other cross muxing needs. For example (POL= L/H, AMSEL=M, EN=H) configuration is for USB SS only muxing while unused diff pairs are left open/Hi-Z. (POL=L/H, AMSEL=M, EN=M) configuration can be used with USB SS and two other independent diff pairs(say two independent 1-lane DP connected to CTX2 and CRX2) if the application chooses to support two independent low res 1 DP lane video with USB3.