Hi,
I have a board , and i have a test program in fpga, fpga sends test packet one after another , and the packet‘s starting data is the same , then the data is increasing(example: the first data is 64'h0102030405060708;the second data is 64'h0203040506070809;the third data is 64'h030405060708090A ,and so on);and packet length is from 100 to 1800 , (emaple : the first packet length is 100 , the second packet length is 200 , the third packet length is 300, the last packet length is 1800 );the gap between packets is 16 bytes ( 2 data time ) .
Now , when fpga starts sending test packets , often , some packets will loss , but the data has no error .
When fpga send the same packet , and the gap between packets is the same , there will not loss packet .
The data flow : FPGA (generating test data) ---> TlK10232 --> Fiber (Loop) --> TLK10232 --> FPGA (check data : data error , packet loss )
Who have some suggestion ? thanks !!!
Best Regards!
08/21/2015
