Hi!
I have a board ,there is a fpga and tlk10232 chip ,fpga sends test data to tlk10232 ,then tlk10232 sends data to fiber ,fiber loops data back to tlk10232 , tlk10232 sends the data back to fpga , fpga detects whether data is equal to the data it sends .
(FPGA<generate test data> --> TLK10232 --> Fiber<Loop back> --> TLK10232 --> FPGA < check the data > );
1.when fpga sends the same packet( the same length and data ),and the gap between packet is 16 bytes (about 2 data time ) ,there is no data error .
2.when fpga sends different packet ,the packet length is increasing from 100 to 1800 (each cycle begins:the first packet length is 100, the second packet length is 200 , the third packet length is 300,---,the last packet length is 1800, and then the next cycle ),every packet data begins from 64'h0102030405060708 , then 64'h0203040506070809, then 64'h030405060708090A,and so on until the end of the frame .and the gap between packet is 16 bytes (about 2 data time).Now ,sometimes ,fpga checks the loopback data , finds some packets have been lost ;because,one packet after another , packet length is cycle ,but its received packet length sometime is jump .
Who has some suggestions ? Thanks !!!
Best Regards!