DS90UB301-Q1　DOUT state of tPLD period

yoshiki hasebe

Mastermind 6385 points

Dear Sirs,

My customer asked us　the following question.

Please tell me the answer to this question.

If immediately after power operates an internal PCLK, which operates externally PCLK from the middle.

Do DOUT is not output in tPLD period after switching to external PCLK?

Best　Regards,

Y.Hasebe

over 10 years ago

0 yoshiki hasebe over 10 years ago

Mastermind 6385 points

Dear Sirs,

There is no reply to me.

Please comment on the above questions.

Best　Regards,

Y.Hasebe

0 Mark Sauerwald88474 over 10 years ago

TI__Genius 13475 points

If on power up, there is no PCLK present, the serializer will operate from it's internal oscillator clock source, which runs at approximately 25MHz. If a PCLK is then presented to the device, then it will switch over to the external PCLK, which will cause a momentary disruption in the output of the receiver as the PLL relocks to the new clock source.

0 yoshiki hasebe over 10 years ago in reply to Mark Sauerwald88474

Mastermind 6385 points

Hello Mark-san,

Thank you for your reply.

I understand your answer.

I will send my customer this answer.

Best Regards,

Y.Hasebe

Interface

Interface forum

DS90UB301-Q1　DOUT state of tPLD period

Interface

Interface forum

DS90UB301-Q1 DOUT state of tPLD period

DS90UB301-Q1　DOUT state of tPLD period