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ESD protection IC

AMAN GUPTA
Prodigy 60 points
Other Parts Discussed in Thread: TPD2E2U06-Q1

HI,

I am looking for ESD protection IC to protect a chip (DUT) fabricated in CMOS 180nm technology.  As the I/O voltage for the DUT cannot be more than 1.8 V, which ESD protection IC will be suitable for this application which can clamp the I/O lines of the DUT between 1.8V - 2V ??

Regards

Aman

  • 0
    Guru 192875 points
    Hi Aman,
    You can use this tool to shortlist a part according to your requirement: www.ti.com/.../emi-solution-products.page

    Regards,
    Gautam
  • 0 in reply to Gautam Iyer
    Prodigy 60 points
    Thanks for replying Gautam. As I can see in that tool, the minimum breakdown voltage is 4V and the clamping voltage will always be more than breakdown voltage. But for my application I need IC with breakdown voltage around 1.8 V.
  • 0 in reply to AMAN GUPTA
    Guru 192875 points
    TI doesn't seem to have a device with a Vbr less than 4V as of now.
  • 0 in reply to AMAN GUPTA
    TI__Genius 12190 points
    Hi Aman,

    An ESD event lasts for about 200 ns, with peak energy over by around 40 ns. Most devices can tolerate a voltage higher than their Max DC rating for such a short time. I good indicator of the needed clamping voltage your device can survive during an ESD event can be obtained from a transmission line pulse (TLP) test. The voltage across the DUT just before the device fails sets the upper limit for what you would need to clamp an ESD event at. I mention this because a TLP test is quite common in device characterization and you may be able to get this information.

    Also, what type of signal lines do you need to protect? Data rates and voltage swings are important to know.

    Thanks and Regards,
  • 0 in reply to Guy Yater
    Prodigy 60 points
    Thanks..... This is quite useful.
    The signal lines I want to protect connects DB9 connector to DUT (CMOS 180nm chip). These lines carry current in the range of mA and voltage swings rail to rail i.e 0V to 1.8V


    Regards,
    AMAN
  • 0 in reply to AMAN GUPTA
    TI__Genius 12190 points
    Aman,

    If these are DC signals then you don't need to worry too much about any capacitive loading by the ESD protection IC and can pick a device with a large diode area. The advantage of this is a lower clamping voltage, at the cost of capacitance. Our lowest clamping TVS isTPD2E2U06 in a SOT (5) package or TPD2E2U06-Q1 in a SOT23 (3) package. These are also low enough capacitance to allow data rates up to 1.5 Mbps. The clamping voltage is about 18V (during an 8-kV ESD event). Just remember that this is a transient voltages, and your process will likely be able to withstand it and you can be sure if you have TLP data for your device.

    Regards,
  • 0 in reply to Guy Yater
    Prodigy 60 points
    Thanks Guy,
    Is there any way to simulate this event in TINA with your IC ? For my DUT I will just use input capacitance and on-chip ESD circuit in simulations .

    Regards,
    AMAN
  • 0 in reply to AMAN GUPTA
    TI__Genius 12190 points
    Hi Aman,

    We do not have a model that supports simulation of ESD.

    Regards,