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TLK2711 SerDes

amnon pomerants
Intellectual 780 points

Hello

Does the TLK2711 must have its GTX_CLK connected to it in case all I want is to work with its Rx functionality, and I don't need to operate its Tx side at all?

If the GTX_CLK is a must even for the Rx side, please explain why.

Thanks

Amnon

  • 0
    TI__Genius 16150 points
    Hi Ammon,

    GTX_CLK is a reference clock which is multiplied by a multiplying clock synthesizer to generate an internal bit rate clock. Hence, this bit rate clock is used by the device's clock recovery circuit to lock to an incoming serial data stream. The serial data is converted to parallel, decoded, and outputted along with RX_CLK.

    Regards,
    Luis Omar Morán Serna
    High Speed Interface
    SWAT Team
  • 0 in reply to Luis Omar Moran
    Intellectual 780 points

    Hello

    I would like please to be sure I fully understood your answer:

    1. Does the TLK2711 generates the Rx_CLK already when the GTX_CLK is provided to it even if the Rx link from the far end is not connected at all?

    2. At this point (Rx link is in active) the Rx_CLK will be locked on the phase and frequency of the TX_CLK?

    3. For the Rx_CLK, will it lock on the far end SerDes CLK already when anything (Comma etc.) will start to appear on the Rx link, or only when Data will appear?

    4. To your knowledge, is there a problem with FPGA DCM (timing module) functionality when its input clock (the SerDes  Rx_CLK) will change from the local 100Mhz (at power up) to the far end 100Mhz (as data starts flowing)?

    5. What is the maximal GTX_CLK frequency difference allowed between the two SerDes?

    Thanks

    Amnon

  • 0 in reply to amnon pomerants
    TI__Genius 16150 points

    Hi Ammon,

    Basically, the RXCLK wil be active as long as the TLK2711 is enabled and a TXCLK is present. So, it is up to the device interpreting the received data to monitor the next signals:

    RKLSB ==> K-Code indicator/PRBS test results.

    RKMSB ==> K-code indicator.

    RXD[15:0] ==> Received data bus.

    And determine wheter or not the data is valid.

    In my unserstanding is no a problem is you change from the local 100MHz (at power up) to the far end 100MHz (data starts flowing) as long as the timing requirements is on spec. 

    For the frequency tolerance the TLK2711 allows ±100 ppm.

    I hope this helps.

    Best Regards,

    Luis Omar Morán Serna

    High Speed Interface

    SWAT Team