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SN75DP122A power sequencing



A search yields nothing.  New board design for Qseven computer modules based on (derived from) Congatec EVAL board with video interface using 75DP122a.  One comparison of Congatec EVAL and our board shows Congatec has 3.3V rail ramp up starting 1 mSec after 5V is up.  Our board has opposite order.  I have added a turn on delay control from 5V rail to a control pin of 3.3V switch controller that does produce such a delay of 3.3V after 5V.  The exact delay I can adjust with a resistor value choice.

My immediate question is are there any known sensitivities to power rail sequencing for 75DP122a?  Then also would 3.3V being up 2 mSec before start of 5V have caused any problem with or otherwise possible damage to the 75DP122a?  Initial sequence happened to come out as 5V started to rise 2 mSec after 3.3V fully up and ramp up (rise 0 to 5V) time is 3.3mSec.


So far the 75DP122a seems to remain in a shut down state.  I can see video into 75Dp122a, around 100 to 200 mV p with a 2 Vdc offset.  There is no signal at the HDMI socket, no DC offset either.  I have checked that all control inputs, CAD_SINK, DP_HPD_SINK, TDMS_HPD_SINK (from pin 19 of HDMI socket), LP#, Priority, I2C_EN, match that on the known good Congatec EVAL board.  Monitor is a Dell monitor connected using a DVI to HDMI cable.  Monitor does have video when connected to Congatec EVAL.  I am using the same Qseven computer module on both boards (move it from one to the other), so using a known good Qseven module.

Any thoughts / suggestions appreciated,

Bill

  • Hi Bill,

    We are not aware of a specific power up sequence requirements, however is common practice to supply power on logic first, then on IO pins.
    In this device 5V powers the logic and DP side, while 3.3V powers TMDS side.
    So, 5V should be applied first, then, when 5V is stable apply 3.3V.
    We have no known failure cases when applying voltages the other way around, but it is a possibility.
    Have you tried a different IC?

    Regards
  • I have today tried another board (first prototypes, only 5 made) with all circuit corrections made first:

    1) pullups for Priority, I2C_EN were to 3.3V, cut track and connect to 5V

    2) add power supply sync control to hold off 3.3V until 5V comes up

    3) add GND connect to DP_HPD_SINK and CAD_SINK inputs, originally pins were open

    With these changes made first, board powers up Ok, video does come on.  On first board changes were made imcrementally, so that did have 3.3V come up stable 2 mSec before 5V ramp up started.  3.3V ramp up time was 1.7 mSec.  5V ramp up time was 3.3 mSec.  A change to couple output of 5V to a control input of 3.3V delays the 3.3V start.

    On first failed board I need to recheck particularly the GND connect to the two inputs to be sure that is good.  It chip still does not have output then it would appear chip (DP122) has failed.  Also note in the present failure state I observe video output pins at HDMI connector are at GND, have no DC offset.  What is your thought as to how this may relate to the failure mechanism?

    Thank you,

    Bill