DF410 Support for 2.5G Ethernet

Hi Matevz,

Are you able to achieve lock with the DS100DF410 at 2.5G? You will be able to view the output of the LOCK_0 to LOCK_3 pins to determine whether CDR lock has been attained. The DS100DF410 is set by default to lock to 10.3125 Gbps and 1.25 Gbps. If you want to lock to 2.5G, you will need to use the DS110DF410 instead of the DS100DF410 for more supported data rate options (see p. 16 of the DS110DF410 datasheet).

Thanks,

Michael

Hi Michael,

we actually only managed to get lock on 10.3125G. Not on 1G not on 2.5G. To get 1G going, we needed to program I2c register 0x1E to 0x9.

So we believed the only way to get 1G (and/or 2.5G) thru is using RAW DATA. If we did not write to register 0x1E, we only got muted signal when putting 1 or 2.5G on input. I will check if it locks to 1G, but I doubt, it would enable 1G retimed signal on output then.

regards,

  Matevz

Hi Matevz,

I decided to split this thread into a new subject so that it can be handled as an individual case.

It seems like what is happening is that the retimer CDR is not able to achieve lock. If lock cannot be achieved, the retimer mutes the output by default. When Raw Data is selected from the multiplexer, the CDR is bypassed, thereby allowing you to get an output signal.

A few questions to help debug:

1. Can you confirm whether you are using a DS110DF410 or a DS100DF410? There are more options available for locking to the right data rate in the DS110DF410 as opposed to the DS100DF410 device.

2. Can you attach a register dump of your programmed settings? We should be able to check whether the settings are appropriate to achieve lock.

3. What is the exact data rate you are trying to lock to? Is it exactly 2.5 Gbps, or is it slightly offset from 2.5 Gbps?

Thanks,

Michael

HI Michael,

we are using up until now DS100DF410. We want to pass 2 signals:
- 10.3125 Gbit/s (10G Ethernet)
- 3.125 Gbit/s (2.5G Ethernet)

We are now waiting to get DS125DF410 which we think will be the most appropriate.

For DS100DF410 we used default register settings + the following:

i2c dev 0
i2c mw 0x18 0xff.1 0xc
i2c mw 0x18 0x1e.1 0x9
i2c mw 0x18 0x9.1 0x20
i2c mw 0x18 0x2d.1 0x86 (this one really changes nothing but the amplitude)
i2c mw 0x18 0xff.1 0x0

We wanted to avoid locking and only putting raw data in case of 2,5G Ethernet thru the chip. But many mysteries happened at that point. Please let me know how I can share scope captures with you.

regards,
Matevz

Hi Matevz,

It has come to my attention at the end of last week that we have been working in parallel internally with one of your contacts, Feras, to resolve this issue. After doing some testing in the lab with the DS100DF10, the best and simplest option to participate successfully in 10G-KR Auto-Negotiation with the DS1xxDF410 retimer is to lock to 10.3125 Gbps data and pass through raw, un-retimed data at 1G and 2.5G rates.

If the retimer cannot lock, then its default behavior will revert to the value of Reg 0x1E. By default, an unlocked state will result in the retimer muting, and I believe this is why the 1G or 2.5G Ethernet rates do not make it through the retimer.

We have found that the following register write sequence will allow you to set the behavior where you lock to 10GbE and pass through 1GbE and 2.5GbE:

Reg 0xFF = 0x0C //Access channel registers
Reg 0x2F[7:4] = 1100'b // Set lock rate for Interlaaken-2 (10.3125 Gbps with Divide-by-1 VCO divider only)
Reg 0x1E[7:5] = 000'b // Output raw data if CDR is not locked
Reg 0x3F[7] = 1'b //This is a reserved bit that must be set to ensure appropriate raw data is output

Once you set these values, the EQ applied at the CTLE is determined by Reg 0x03. You can change the EQ if desired (though the signal quality should already be reasonable at the 1G and 2.5G rates) by setting Reg 0x2D[3] = 1 to enable EQ overwrite. You can then set the EQ overwrite value in Reg 0x03.

Thanks,

Michael

Hi Michael,

thanks. What a small world. Shortly after I posted my last question to you I received answer from Feras. That helped and we got 10GKR AN going (2,5G Ethernet).

I have posted some additional questions to Feras, so I will not repeat them here. In case you find them interesting for the general public here, you can post the answers also here.

We played with bits in 0x27, but we had no idea about 0x3f, so it is clear why it did not start.

Thanks,

Matevz

Hi Matevz,

Glad to hear that things are starting to work! We'll work with Feras through our e-mail thread to follow up with you on any questions you may have regarding this in the future.

Thanks,

Michael

Hi,

We have some problems to operate 1GbE with DS100DF410.

I tried to configure those registers, and suddenly works writing on the last Reg 0x3F[7] = 1. What is the specification of this register, because the datasheet is a reserved register (without any comments/description)?

Thanks!

Érico Sawabe