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TMDS181 Documentation Feedback

Other Parts Discussed in Thread: TMDS181, TMDS141, TPD12S521, TPD12S520

The TMDS181 parts are not yet available but a nice first public draft for the data sheet is accessible (http://www.ti.com/lit/gpn/tmds181). The Documentation Feedback form is very small and provides few formatting options so it'll be more convenient to share the findings here. My notes about the document are as follows.


Page 1:

The figure "Simplified Schematic" is of too small scale. it's OK for the on line document but on a printed pdf version this diagram looks too tiny to be recognized by the reader's eyes. Perhaps it'll make sense to remove this figure seeing that there is the full-scale drawing on the page 25.

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Page 5, paragraph 6.1 Absolute Maximum Ratings:

The pin is referenced in the table as "TEST/A1". Meanwhile that pin is mostly referenced within the document as "A1".

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Page 10, paragraph 6.8 DDC, I2C, HPD and ARC Electrical Characteristics:

1. The table describes the values, which are related to the part's performance. But some rows actually about the parameters that are related to operating conditions rather than performance. For instance, look at the row 1: Vil (SCL/SDA_CTL, SCL/SDA low level input voltage). It's the operating condition so the value does not depend on the part's performance. Meanwhile there is the table on the page 6 that is specifically dedicated to the recommended operating conditions. From my point it'll make sense to harmonize that two tables moving those conditions-related parameters (such as input voltages) from the Electrical Characteristics table to the Recommended Operating Conditions table in the paragraph 6.3, page 6. Another option would be to leave them in the Electrical Characteristics table but to relocate to the "TEST CONDITIONS" column.

2. The table does not provide the value for low level output voltage for SCL/SDA_SNK pins.

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Page 19:

The Figure 15. HPD Test Circuit is not referenced within the document. I presume it's supposed to be mentioned in the table on the page 10 as a test condition for the HPD pins. Another suggestion is to replace the markings on the figure from "HPD Input" and "HPD Output" with "HPD_SNK" and "HPD_SRC" respectively.

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Page 27, paragraph 8.3.5 TMDS Inputs Debug Tools:

The hope is the next document version will discuss the pattern generating stuff in more details giving the users an idea for what's the real benefit from that feature and how to use it.

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Page 32, paragraph 8.4.4 DDC Functional Description:

1. There is the statement "The HPD goes to high impedance when VCC is under low-power conditions, <1.5 V". The HPD line does not belong to the DDC bus defined by the VESA's E-DDC Standard document. So think about moving that statement from the DDC-related paragraph elsewhere.

2. I'm not sure the document provides enough coverage for the DDC buffer. There are bi-directional I2C drivers and certain important considerations seems missing. For instance, look into the data sheet for TMDS141. There is the following statement in the "I2C Function Description" section: "When the T side is released by the external I2C driver, driver T is still on, so the T side is only able to rise to the VOL of driver T. Driver R turns off, since VOL is above its 0.4-V VIL threshold, releasing the R side. If no external I2C driver is keeping the R side low, the R side rises, and driver T turns off once the R side rises above 1.5 V, see Figure 20. It is important that any external I2C driver on the T side is able to pull the bus below 0.4 V to ensure full operation. If the T side cannot be pulled below 0.4 V, driver R may not recognize and transmit the low value to the R side". I presume something like this may be applicable to TMDS181 part as well.

3. In certain applications, it's highly desired for the part to have dedicated OE input for the DDC buffer (similar to what is implemented in TMDS141). So the fact that TMDS181 does not have that input seems a bit disappointing.

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Page 33:

1. The pin is referenced in the text as "TEST/A1". Meanwhile that pin is mostly referenced within the document as "A1".

2. The "LEGEND" string below the Figure 31 defines never used abbreviations: "R=Read only; -n=value after reset".

3. There is the statement "The local I2C is 5-V tolerant, and no additional circuitry required". Meanwhile, according to the table "Absolute Maximum Ratings" (page 5), the max. input voltage for the SDA/SCL_CTL pins is equal to 4 V.

4. There is the statement "The following procedure is followed to write to the TMDS181 I2C registers:". Consider re-wording.

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Page 34:

1. There is the statement "When no sub-address is included in a read operation, the TMDS181 sub-address increments from the previous acknowledged read or write data byte". That statement can unintentionally cause a reader to wrong conclusion that there is some way to explicitly specify the sub-address during a read operation. To eliminate such risk, I suggest to replace "When" with "As" resulting in the statement "As no sub-address is included in a read operation, the TMDS181 sub-address increments from the previous acknowledged read or write data byte". Beside of that, it's not clear from the text what will happen with the sub-address pointer after the last register reading (of the address 20h). There can be two scenarios: A. the pointer has automatically wrapped around to 0. B. the pointer has incremented as usual resulting in the value of 21h so the controller will have to take care about clearing it before the next read cycle. The document don't says what's the case.

2. There is the statement "Writes to a reserved register that is marked with ‘W’ produce unexpected behavior". The problem is that there are no reserved registers marked with ‘W’.

3. There is the statement "A table of bit descriptions is typically included for each register description that indicates the bit field name...". Looks confusing. Not the whole table is included, just a tag(s) defined by the table. Consider re-wording.

4. Table 4. Field Access Tags: The tags "C" and "NA" are never used.

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Page 35, Table 6. MISC CONTROL Field Description:

1. The last row in the table: There is the statement in the "DESCRIPTION" column: "When returning from various modes of operation, need to toggle the power setting from 1 to 0 then back to 1 for...". It is not clear what exactly is the "power setting" to toggle and how to do so.

2. The description for "APPLY_RXTX_CHASNGES" field: It'll be less confusing to refer the exact field names. E.g. "TX_TERM_CTL" instead of "tx_term", "HDMI_TWPST1[1:0]" instead of "twpst1", etc.).

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Page 36, 4-th row of the Table 6. MISC CONTROL Field Description (continued):

The description for TMDS_CLOCK_RATIO_STATUS field states that "This field is updated from snoop of I2C/DDC write RWU to slave address 0xA8 offset 0x20 bit 1 that occurred on the SDA_SRC/SCL_SRC interface". According to the functional block diagram on the page 25, TMDS181 snoops on the sink side of its DDC buffer. So I suspect there is a typo and the correct statement reads "... occurred on the SDA_SNK/SCL_SNK interface".

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Page 37, the last row in the Table 7. Equalization Control Register Field Description:

The parameter "VOD" is mentioned in the "DESCRIPTION" column. To be consistent, it'll be better to replace each that entry with "Vod".

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Page 38, Table 8. RX PATTERN VERIFIER CONTROL/STATUS Register Field Description:

1. For all bit-mapped fields (PV_SYNC[3:0], PV_LD[3:0], PV_SYNC[3:0], PV_FAIL[3:0], PV_TIP[3:0], PV_DP_EN[3:0], TST_INTQ[3:0] and TST_INT[3:0]) the exact bit-to-lane relationships are not provided. One can guess that bit 0 is related to the lane 0, bit 1 - to the lane 1 and so on but there is no official definition. Moreover, it's not clear if the lane swap function affects that mapping.

2. The values for PV_THR[2:0] and TST_SEL[2:0] fields are not defined.

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Page 39, the last but one row in the Table 8. RX PATTERN VERIFIER CONTROL/STATUS Register Field Description (continued):

The values for "ARC_SWING" field are not defined.

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Page 41, Figure 32. TMDS181 in Source Side Application:

1. The VSADJ pin resistor value is equal to 7 kOhm. Meanwhile the paragraph 8.3.10 TMDS Outputs (see page 29) and Table 9 (see page 42), both recommends the value of 7.06 kOhm.

2. Two decoupling caps for Vcc are of 0.01 uF. I suspect it's a typo and the correct value is 0.1 uF.

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Page 44, Figure 35. TMDS181 in Sink Side Application (Including 5-V Implementation):

1. The VSADJ resistor's value is equal to 7 kOhm. Meanwhile the value of 7.06 kOhm is recommended as a starting point in the paragraph 8.3.10 TMDS Outputs, see page 29).

2. Two decoupling caps for Vcc are of 0.01 uF. I suspect it's a typo and the correct value is 0.1 uF.

3. In the "5V HPD Implementation" frame the source terminal of one transistor is left floating. I suspect it's a misprint and the terminal is actually grounded.

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Page 45, Figure 36. TMDS181 in Sink Side Application:

1. The VSADJ resistor's value is equal to 7 kOhm. Meanwhile the value of 7.06 kOhm is recommended in the paragraph 8.3.10 TMDS Outputs, see page 29).

2. Two decoupling caps for Vcc are of 0.01 uF. I suspect it's a typo and the correct value is 0.1 uF.

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Page 47, paragraph 9.2.3.1.2 Compliance Testing:

The header reads "I2C control for HDMI1.0a and HDMI1.4b". I suspect it's a typo and the correct header reads "I2C control for HDMI2.0a and HDMI1.4b".

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Page 49, Figure 38. Recommended 4- or 6-Layer PCB Stack:

On the left picture the numbers for laminate layers thickness are specified while on the right picture are not. To be fair, it'll be a good idea to provide the respective numbers on the right picture (6-layer stack) as well.

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Page 50, Figure 39. Layout Example – Source Side:

1. The pin is referenced as "TEST/A1". Meanwhile that pin is mostly referenced within the document as "A1".

2. The position of the "TEST/A1" label is not aligned with the respective copper trace.

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It is stated in the section 9.1 Application Information that "The TMDS181 is also capable of working in an active cable to extend the cable length even further". It'll be nice to see the register settings guideline for such applications.

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It'll be nice to see in the section 9.1 Application Information a mentioning about the necessity of a ESD protection device on the HDMI terminal. Especially as TI does offer such devices (e.g. TPD12S520/TPD12S521 or a future versions of them with support of HDMI 2.x). BTW, for the time being the HDMI2Cx-14HD parts from ST looks superior.

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regards,

    Igor