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FPD-Link III Lock

Tom Saluzzo
Expert 1280 points

Using the FPD-Link III.  I have my setup almost working (streaming SD video, sorta) with the 91xA eval boards.  Problem is that my LOCK status is not consistent.  Do you know what sorts of things can effect that? 

 

I have the eval boards in default factory setup: I2C and power backchannel, connected over 1.5ft RG-174 coax with the correct FAKRA crimp ends, using an imager PCLK at ~27MHz (SD video ADC).  LOCK status is mostly HIGH, but will occasionally go low, causing the video to roll constantly.  I was getting worse than 25% LOCK status before (dim, briefly blinking LED), and adding 15pF to 30pF shunt to the serializer PCLK input line made it better, but not 100%.  My imager PCLK has tested fine without the FPD-Link, so I’m not sure what the issue is for the serializer input (rise time? shape?). 

 

PCLK serializer input is 100%, but the deserializer output drops out when it loses LOCK.  See my attached scope image.  Top CH is deserial PCLK output, bottom CH is LOCK status (active high).Print_1.docx

 

Without any PCLK input from imager, LOCK is 100% and PCLK output is 50MHz just like the datasheet describes.

 

I hope you can shed some light on this.

  • 0
    TI__Genius 13475 points
    Tom
    I would suspect an issue with the quality of your PCLK. If there is excessive jitter on the PCLK, then the deserializer will have a hard time maintaining lock. The devices are not sensitive to low frequency jitter (<f/40) or to very high frequency jitter (>f/20) - so in your case, with a 27MHz PCLK, the region that you need to be most careful of is from ~500kHz to a bit over 1MHz. What is the source of the PCLK that you are using?