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TLK10232 for initialization order of the opposite configuration

Hideo Tsutsui
Prodigy 140 points
Other Parts Discussed in Thread: TLK10232

Hello

It's now tested with the following configuration.


■ Configuration
· Case1 (LoopBack)
   Board # 1 [FPGA (XAUI) → TLK10232 (10G-KR)] → Cable
                                                                                        ↓↓ (LoopBack)
   Board # 1 [FPGA (XAUI) ← TLK10232 (10G-KR)] ← Cable

· Case2 (facing)
   Board # 1 [FPGA (XAUI) → TLK10232 (10G-KR)] → Cable
                                                                                        ↓↓
   Board # 2 [FPGA (XAUI) ← TLK10232 (10G-KR)] ← Cable


■ Q1
Therefore, in Case1 and Case2, when carrying out the initialization (Link training, AutoNegotiation, etc.), because the configuration is different, whether you need constraints such as access procedure?

■ Q2
During initialization in Case2, or Board # 1 and the Board # 2 There is a problem to implement simultaneous?
If the problem certain way, the access method used in Case1, like the Board # 1⇒Board # 2, is scheduled be conducted in order.

Thank you will please more.

  • 0
    TI__Genius 16150 points
    Hi,

    We are checking your question, I´ll be back with the answer.

    Regards,
    Luis
  • 0 in reply to Luis Omar Moran
    Prodigy 140 points
    Hello, team

    I have a question in addition.

    ■ test configuration
    Configuration 1 (cable wrapping)
    Board # 1 → (10G-KR) → coaxial cable → (10G-KR) → board # 1

    Configuration 2 (normal operation)
    Board # 1 → (10G-KR) → E / O → optical fiber → O / E → (10G-KR) → board # 2


    ■ Q3
    When normal operation (Configuration 2), in the board # 1 and # 2 board, auto-negotiation and link training, respectively, Is recommended procedure to implement and in what order?

    Draft 1 (one side LoopBack state)
    ① to board # 2 (HS side Loop-Back) state, the board # 1 side, AN / LT implementation.
    ② on the board # is in 1 (HS side Loop-Back) state, board # 2 side, AN / LT implementation.

    Draft 2 (normal operation state)
    ① board # 1 (HS_TX side setting) → like a board # 2 (HS_RX setting), set the board # 1 and # 2 board alternately, I read also training result alternately.

    Best Regards