Using SERDES for Muxing/Demuxing 12, 3.3v LVCMOS signals from one board to another at a distance of 1meter

Hi Mamatha,

It is quite possible to use a SerDes to accomplish this function.  I would look at the DS92LV16 device.  It can serialize/deserialize 16-channels into one LVDS differential pair.  One meter of distance is quite common for this device.

When transferring clocks across this type of interface you will need to consider the frequency relationships so that the result is stable on the receiving side.  Driving the Serializer input clock with a source which is synchronous to your "data" clocks will be necessary to achieve a stable output on the deserializer side.

There is more to consider with the serializer-deserialier arrangement, but the benefit is a much smaller cable and most likely lower EMI.

Regards,

Lee

Hello Lee,

Thank you for providing me the required information. I will go through the DS92LV16 datasheet.

Thanks & Regards,

Hello Lee,

I am  now evaluating the IC DS92LV18  using the LVDS-18B-EVk so that we can incorporate the IC in our FINAL design.

I am using 2 EVKs, one as Serializer and another one has Deserialzer. To Serializer I am feeding PRBS data generated from FPGA  on one pin and PRBS clk (10MHZ, used for PRBS generation) on another pin from FPGA. From the deserialzer  the respective pin are connected to  PRBS detector running in the another FPGA.  60MHZ clock(generated in FPGA)  is given as  serilaizer clk  and 10MHZ TCXO is connected to the FPGA. With this setup, PRBS detector is indicating mismatch in the received pattern from the deserilazer and also we are observing that there are  glitches on the Deserialzer clock as well as on the PRBS data and PRBS clock(10MHz) at the desirailazer output  . Kindly let me know what could be the reason for the same.

Regards,

Mamatha

Mamatha,

Connect 60 MHz clock from FPGA to transmit TCLK.

Connect 60 MHZ clock from FPGA to receive REFCLK

Connect PRBS to DIN0 on Serializer

Connect PRBS 10 MHz clock to DIN1 on Serializer.

Tie the rest of DIN[17:2] = GND

Initially use the SYNC pin to ensure a valid lock condition and then try the data.  Since so many data are unused, the DS92LV18 may be false locking due to the pattern content.  See pages 12 and 13 in the datasheet.

www.ti.com/.../ds92lv18.pdf

Best Regards,

Lee

Hello Lee,

Thanks for inputs. I did the test set up as per your inputs but still PRBS is detetcting errors. It is also observed that glitches are occuring periodically.

find below the table reflecting the Serializer frequency and the
frequency of error occurence

Serializer frequency      Frequency of occurence of error

40MHZ                                         1.225KHz
60MHZ                                          2.4390KHz
57MHz                                          694.44Hz

I feel it is something related to framing boundry  of the serializer and Deserialzer.
 I am using SERDES for the first time and my project is time critical hence kindly help me resolve this issue. 
Can I rely on SERDES to carry time critical signals from one board to another board which are located 1m apart.

Mamatha,

Please confirm that using SYNC allows the DS92LV18 to acquire and maintain lock.

Is the clock frequency used by the FPGA the same clock as the serializer TXCLK?  It could be the timing relationship between the FPGA output and the TXCLK rising edge.  See Figure 7 in the datasheet.

Regards,

Lee