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SN65DSI84 DSI input issue

James Huang3
Intellectual 330 points
Other Parts Discussed in Thread: SN65DSI84

Dear Sir,

My customer using SN65DSI84 right now. They have two questions

1. If DSI signal quality is not good, does SN65DSI84 have LVDS output?

2. Does SN65DSI84 have register could indicate DSI signal quality?

Thanks

BR 

James

  • 0
    TI__Mastermind 18655 points

    Hello James,

    If DSI input is being affected by the EMI/noise, try to adjust the EQ value at addr 0x11.  Default is 0x00 with no equalization, try 01b or 11b and see if the issue improves on both DSI_DATA and DSI_CLK

    If there's noise issue on LVDS output/panel input, the LVDS_VOD swing can also be adjusted at addr 0x19. 

    There are error reporting registers that the system software can read to help with system debug. The error status registers are at offset 0xE5 and/or E6. Individual error conditions at address 0xE5 and/or 0xE6 can be reported via IRQ pulses by enabling the corresponding error status bits at offset 0xE1 and/or 0xE2. Refer to the datasheet for details in the IRQ operation and the error reporting mechanism

    Regards

  • 0 in reply to Joel Jimenez0
    Intellectual 330 points
    Hi Joel,
    Thanks for your reply. My customer wants to know as below.
    1. If 0xE5=01 or 8D. What does it mean 01 or 8D. Does it will let LVDS output abnormal.
    2. What is correct value about 0xE5.

    Thanks

    BR
    James
  • 0 in reply to James Huang3
    TI__Mastermind 18655 points
    The default value of the 0xE5 register is 01. If you are getting 8D after reading 0xE5, it indicates that the device has detected error in the DSI inputs.

    FYI, init sequence as below:
    1. After power is applied and stable, all DSI input lanes including DSI CLK(DA x P/N, DBx P/N) must be drive to LP11 state.
    2. Assert the EN pin.
    3. Wait for 1ms for the internal voltage regulator to stabilize.
    4. Initialize all CSR registers to their appropriate values based on the implementation.
    5. Start DSI video stream.(init seq5).
    6. Set PLL_EN = 1
    7. Wait 3ms for PLL to lock.
    8. Set the SOFT_RESET bit

    Could you please provide an dump of the registers and the panel datasheet?

    Regards,
    Joel