SE0 state not achieved - TUSB1210

I use the same board as given by TUSB EVM gerber files and connect it to Spartan 6 FPGA Kit...

Although I program it as device mode, but I have used an OTG connector and ID pin is also connected.

Is this what is creating trouble may be???

have connected the ID pin to ground, still the same problem.

please help if possible.

Hi,

Does any one reply here? Is there something unclear in my post please tell?

Or am i on my own in this?

Regards.

I have also asked a few questions, including one where the PHY gets into a "locked" condition. None have been answered, despite initial threats that someone in TI would be able to help.

My presumption is that the TUSB1210 was designed a long time ago, by people who have either left, or by a contracted party. In short, don't hold your breath if you're waiting for an informed response.

For information, I'm in a similar position, but after trying the TUSB1210, I redesigned my board to take the MicroChip USB3320. This is really fill-in work so progress is rather slow but at least it's now in a forward direction.

I wish you good luck, and I'll continue to lurk here to see if anyone actually gets any help with this device!!

Hi Mike,

I have seen your posts, I wish I had seen them b4 designing my boards etc. then I would have kept all my options open but now I have spent quite a bucks on it.

But there is one thing I want to ask, I have found that DIR signal becomes high for TUSB1210 more than often, whereas on chipscope I do not find any change in RXCMD. Why does DIR remain high then? Again I also find that raising stp still does not make DIR low. Why is it so?

Did u find any soln to it?

Regards

I moved to the USB3320! So far so good!

I don't recall any issues with DIR going high.

To be honest I don't see it as a problem as all the PHY is doing is updating the information you already know.

Sorry, you say DIR stays high after a RXCMD?

Hi Mike,

I will tell you:-

When I execute the below steps:-

Apply reset for more than 200ns.  The PHY will pull DIR high to ensure the Link will not drive data lines.

Wait for DIR to go low.

Wait for a RXCMD, ie a toggle of the DIR pin.

 

The peripheral must start as a FS device by pulling DP high through an internal resister controlled by FUNC_CTRL register. First we must disable OTG features by writing x”00” to the OTG_CTRL (x”0a) register.  A TXCMD byte of x”8a” is sent then a data byte of x”00” as per Figure 1.

 Send x”45” to FUNC_CTRL (x”04”) where this sets the peripheral device in the Fast Speed mode by making D+ high and D- low ( LineState “01” – J).

Now after executing above steps I get RXCMD indicating a state J but then DIR Remains high here after. DIR still remains high after detecting SE0 from the host side. If DIR is continuous high, how do I write the next set of commands such as Chirp 'K' and NOPID in order to generate Chirp K signal to Host. This is where I am stuck.

I am developing device side PHY and Link when i raise the above doubts, This is FYI. A help extended will be thankful in this in case you have some time.

Regards.

 

Attached is the chip scope waveform :-

During DIR low, I write TXCMD RegRDWR - 8Ah,00h and 84h,45h to disable OTG registers and set the device PHY in peripheral mode to give J state given D(0) = '1'. Here after DIR never goes low, even after detection of SE0 from the host side. So how do I write the next set of commands is my problem. I have even raised STP but does not make situations any better..

Regards.

There is one more thing that I have found which is that my VBUS VALID in RXCMD is always '0'.

Hello,

I have few comments here:

(1) By D(0) , do you mean D+ line?

(2) While performing this test, have you kept your cable connected to USB Host? I am asking this because without VBUS, I would not expect J state on D+/D- line unless you have not used VBUS coming from Host to connect to VBUS pin of PHY chip. 

(3) Although not logical, you can give some time duration between two register write operations. Just a try to see does this make any difference.

Thank you,

Bhaumik

D(0) means data bus LSB of ULPI which gives the state of D+;
yes the host is connected...

Ok I will try, thanks..

Hi,

You have shown one Chip-scope image, In that, there is one signal having name D(0). If this signal is Bit 0 of ULPI Data bus, then there seems some mistake. Because when you write 0x45 (Hex) value, bit 0 of ULPI data must be high. But in your case, that is not high during register write operation. It goes high only after some time once you write data in Function Control register. In short, please ensure that you are driving correct dara on ULPI data bus.

Regards,

Bhaumik

 

Hi Bhaumik,

Thanks for analyzing waveform in depth. Actually I have renamed some signal that shows the J state of Line i.e. D+ as D(0) for highlighting the main problem that I am facing.

Actual D(0) is high when I am writing the data. When I write the value 45X, DIR becomes high and then I find J state of the signal of the ACTUAL D(0) which I have latched and shown as D(0) [You can call this Dummy D(0), the one shown in the waveform].

Here after I keep on monitoring DIR, It never becomes LOW, even If I assert STP for one clock cycle.

The project is in a standstill stage.. lot of trouble because of this..

Regards.

Hello,

You mentioned that DIR does not go low when you assert STP for one clock cycle. Could you try by asserting STP high for more time (10 ms - mili second.)? I think in that case DIR would go low. If you try this, please let us know result.

Regards,

Bhaumik

Can I keep the STP ='1' asserted and monitor DIR to go low. Can I do it this way?

Yes.

Hi Bhaumik,

This is what is happening:-

When I detect SE0, I monitor SE0 for 2.5uS steadily and then I drive STP = '1' continuously and monitor for DIR = '0'. The moment I get it [around after 200us] I drive TXCMD - 84h followed by 54h to convert to HS mode. I find that DIR goes high before I even raise STP = '1'. See the snapshot:-

Now I drive STP = '1' again or else I do not get DIR = '0' at all. Again after 200uS, I get DIR = '0' and I drive TXCMD NOPID to initiate K chirping  - i.e. 0X40 followed by 0X00,

Hereafter I see NXT = '1' after a long time in a toggling way and it becomes LOW after DIR = '1' goes high. It does not wait for any STP = '1' signal as shown below:-

What happens after this is that dir starts toggling in a periodic manner indefinitely as shown below to give you the complete picture:-

I do not get CHIRP 'K' on the line.

ONE IMPORTANT THING WHEN DIR is HIGH, I ALWAYS GET :- 0X00 or 0X80 on the Lines. IS IT OK????

Regards...

OK, I send 0x40 to the FUNC_CTRL to power up the device before sending anything to the OTG_CTRL register.

Not sure if that should make any difference though. Suggest you try and that and come back.

BTW most PHYs have nearly identical footprint, so not difficult to spin your board to take another device.

Can you explain D(0)? Are you assuming that any byte with DIR high and NXT low is a RXCMD?

Regards

Mike

Ignore my post, I was answering a much earlier reply and my browser didn't see the latest posts despite refreshing.

Hello ARM arm,

Although you tried very well to explain your scenarios, I am not able to clearly get idea. Anyway, here are few comments from my side.

(1) I asked you to drive STP for some what larger duration. That was just for testing purpose. This should not be required during normal operation.

(2) At the beginning you told that you are not getting SE0 state. I would like to know what changes have you made that help you to detect SE0 state on line state?

(3) Regarding your screen-shot 1 ( where DIR goes high before STP is asserted while writing 0x54 ), This may be the case of Register write aborted by PHY chip. Please have a look at section 3.8.3.2 and 3.8.3.3 from ULPI Specification v1.1.

(4) According to me, behavior which you are getting ( considering your screen shot 1), is not expected. PHY chip should not drive DIR high for this much time. Because Data (0x00) driven by PHY chip is same for this entire duration. PHY chip should drive RXCMD only when something has changed.

(5)  I request you to verify your schematic one more time. I also request you to check logic which you have written in Verilog (or VHDL) to drive ULPI interface against ULPI specification.

(6)Few more items to be checked :

• Are pin assignments okay?
• Data line is bi-directional. So are you driving it only when DIR is low?

(7) Also are you designing it your self? Or have purchased it from third party? If you have purchased it from other party, those design engineers could help you solve your problem

These are just my thoughts. You may have better idea regarding your design.

Thank you,

Bhaumik

Hi bhaumik,

Thanks for the detailed reply. You know there is one thing that I am observing which is :-

Whenever I find DIR toggling in a repetitive manner, I find that the VDD1.5V supply of TUSB1210 goes to 2.0V. In case it does not, the supply remains at around 1.61V. I am doing some testing and will let you know in complete how things shape up.

But for initially, we are using EVM gerber for TI, generated the board and using it in device mode so i do not think there is design issue. VHDL implementation, we are very strong at and pin assignment or data line bidirectional whether used properly or not [tristate etc.] are not there.

I will update you as this power supply issue and the comment made by you that DIR should not remain high has left me thinking as to where can be the trouble.

You know even after power on reset, i.e. resetb, DIR once come low [where are stuff my commands in order to get line state J] and then remains high permanently unless I use STP = '1' for long time.

First of all can you confirm that you have a 2.2uF or greater cap on the Vdd1.5V supply.

For this rail to go high and I'm assuming it isn't powering anything external, it implies some form of internal contention or mismatch of driving signals/strengths. This is something I have never felt the need to check but sounds very wrong.

Can you confirm all the other voltages are in range, and that you are genuinely driving ALL of the IO at the CORRECT IO voltage?

Have you tried setting the device power on bit in the FUNC_CTRL register before sending the OTG_CTRL register any data?

As Bhaumik intimated, I would recheck your design and implementation.

Hi Bhaumik and Mike,

Yes, I have checked CAP on 1.5V in 4.7uF and it is OK.

My power up sequence is as follows, I am detailing power up sequence only cause here is where I guess there may be some issue:-

1) I keep resetb low and STP ='1'. My CS is always tied to 1.8V.

2) When I check for DIR high, I wait for 3ms  and then RESETB  = '1' along with CLK = 60MHz.. Here many times I find that VDD15 = 1.9V [PROBLEM]. DIR Some times even stucks at one and does not come low at all even though STP remains high

Why VDD15 goes beyond limit and why DIR does not come low - PLL Does not lock or what??

I have checked other voltages - fine - 3.3V and 1.8VDC. My VDD33 and VBAT sre shorted externally. I have even changed the chip twice, same results.

I switch on 3.3V and then 1.8V through two separate switches one after the other.

I will start a separate thread for this as well, you may reply there..

Regards.