I'm looking for a Gb Ethernet PHY with RGMII interface and found the DP83867IR. In the short overview on page 1 of the datasheet it mentions IEEE 1588, and the only other reference to this is a short description of the possibility to generate an SFD pulse on one of the GPIOs.
This will generate a pulse for each package that comes through the PHY in both directions, which can become quite a lot in a busy Gb network. There are however a lot of pattern match registers and a register where you can see if the pattern was matched.
I want to match IEEE 1588 messages for only the domain that I'm setup to use and my understanding is that I will be able to setup match data and masks specifying what must be matched, which should work. Is this right?
Is it possible to also have the match bit put out on a GPIO? With the SFD and the match bit on GPIOs I will be able to use my fpga for precise timestamping and only save the timestamps that are relevant for my domain, which is exactly what I'm looking for.