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[DS90UB925Q] VSYNC restriction

Other Parts Discussed in Thread: DS90UB925Q-Q1

Hello~

According to DS90UB925Q-Q1's datasheet page 16, VS signal has one restriction as below.

"VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles."

Does It mean that "case I" is illegal and "case II" is right signal as below picture??

In other words, "case I" is 2 transition per 130 clocks, and "case II" is 1 transition per 130 clocks.  Am I correct??

Thanks... C.W. :)