We'd like to use these parts to transmit 4 non-return-to zero serial data streams from pt A to pt B. The data streams are 8-channel TDM formatted serial data from audio A/D's (CS5368's). We can guarantee perfect DC balance by transmitting each stream and its compliment, plus a frame clock and its compliment, thereby using all 10 bits.
The concern is that because TDM data streams can look very similar to each other, particularly at low audio levels where the 2's compliment coding yields a serial stream that sits right at the 00000...00000 - 1111...11111 transition pt. The frame signal runs at 1/256 the clock rate which also creates a static pattern in the data running at 1/256 the input word rate..
Forced sync is probably the way to go.
The question is: assuming the link is synchronized at power up and assuming the embedded start/stops stay in the expected spots, will RMT patterns make the part susceptible to false lock?
The signals can be arranged any way. For example, to eliminiate an extended 01 or 10 pattern, the signal and it's compliment can transmitted on non-adjacent bits. Likewise the TDM1,2,3,4 can be on adjacent bits followed by the 4 compliments. Producing (sometimes) a 1111/0000 pattern. Not sure if that's better or worse.
Thanks
-Joe
