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DS90UB901Q/DS90UB902Q

Joshua Booth
Prodigy 10 points


Hey guys,

We seem to be having some issues with a DS90UB901Q/DS90UB902Q pair. For the most part it works. A constant 100% clock is established and up to 4 data lines can be used. When more are used the lock drops periodically 80-90% and the PASS pin on the deserialiser fluctuates.

So mainly two questions here:
1) Any ideas on why increasing the input lines that are switching causes the lock to drop?
2) The datasheets imply the PASS pin should be High during correct operation. However when it works for us it is 100% low whilst the lock pin is 100% high.

  • 0
    TI__Expert 5210 points

    Hello Joshua,

    This is common and also what we sometimes see in the lab when debugging FPD-Link systems. Depending on the pattern your are sending through your FPD-Link Ser/Des pair, this will also depend on which LVCMOS data lines are becoming corrupted. If the pattern is more complex and involves many transitions, you will see more lines erring. If the pattern is simple (i.e. all 0's), less lines will have errors.


    The problem however, is independent of the pattern. If the part is still LOCKing but you are seeing bit errors on the forward channel, there are a few suspects:


    1. Layout - Were proper layout guidelines in the datasheet and EVM User's Guide followed? LVCMOS Input and Output traces should be 50 Ohms single-ended for best signal integrity. Also, are you using current damping/impedance matching series resistors on these lines? Layout for the high-speed FPD-link traces (DOUT, RIN) should be 100 Ohms differential and not terminated externally(100 Ohms termination is internal to our chips).

    2. Cable Type - what cable are you using? Is it shielded? Is it automotive grade (i.e. low loss)? For shielded twin pair (STP) applications we recommended Leoni Dacar 462.

    3. Schematic/General Operation - Do power supplies come up before PDB pin on both Serializer and deserializer boards? Are you operating in the correct MODE? What is the PCLK input jitter into the 901Q device? What is the system FPD-Link input jitter coming into the 902Q device? Looking at an eye diagram on CMLOUT will help you determine if you have an eye opening that meets the eye width and height specs listed in our datasheets. A closed eye means loss of LOCK and/or errors.

    -Sean