We are using an FPGA (homebrew not a core) as a reduced functionality MAC for the DP83848. For testing it we are are using it in RMII mode half duplex and we are looping the TD+ to RD+ and TD- to RD- on the same PHY (through a transformer of course). When we run in 100MBPS mode we see the data going out at TXD0 and TXD1 and the same data coming back on RXD0 and RXD1 and it works just fine.
However when we try to run in 10MBPS mode the Data coming back on RXD0 and RXD1 is swapped from TXD0 and TXD1 (TXD0 data is coming back on RXD1 and TXD1 data is coming back on RXD0)
Do you have any idea what would cause this to happen?
Thank you