The datasheet has the following statement on the first page.
"Programmable MII/GMII/RGMII Termination Impedance"
Is this to be understood as output impedance?
I haven't been able to find any settings or registers to control this impedance. I'm asking because we have to run our RGMII bus through an analoug switch which puts extra load on the signals. This load together with the "normal" output impedance of a PHY makes it impossible for us to match timing on an fpga. If we could lower the output impedance we could hopefully counteract the extra load.
There are also other interesting things/features of this PHY but this is right now the most important.
Thomas