Full HD with DS90C387/8

Hi,

Thanks for your patience, as we were out on holiday in the U.S. this past week. I do not think this will work with the operating clock frequency you are designing for.

The reason is because of the supported clock frequencies for this chipset. Since your input and output appears to be 48-bit dual pixel 24-bit color, you will be operating in the context of the supported dual pixel rate:

Maximum supported dual pixel rate for DS90C387 = 112 MHz
Maximum supported dual pixel rate for DS90CF388 = 112 MHz

The 170 MHz clock support mentioned in the datasheet is only for single-to-dual conversion on the Tx serializer side. This function will take in single-pixel 24-bit data that is clocked at up to 170 MHz and covert the serialized outputs to odd/even dual pixel data at the TxCLKIN rate divided by 2. Therefore, the output LVDS clock rate for this single-to-dual conversion operation is 170/2 = 85 MHz maximum.

Since your desired input clock is 148.5 MHz, the DS90C387/DS90CF388 chipset will not be able to support this dual-pixel clock frequency. I did a quick scan of other products offered that support dual-pixel clock support, and I could not find any LVCMOS-to-LVDS SerDes that support this need.

Thanks,

Michael