SATA Redriver

Hi Jacek,

We have these devices for SATA supporting up to 6Gbps:

SN75LVCP600: Temperature range 0 to 85

SN75LVCP600S: Temperature range -40 to 85

SN75LVCP601: Temperature range 0 to 85

The measurements we have for these devices are on FR4 no using cables.

Regards

Thanks Michael,

DS64BR111 looks promising for my application - Do you have apps note describing a typical application using resistors for 4 - 5m of SAS SATA cable? I am trying to get the loss number for cables of interest.

Thanks,

Jacek

Hi Jacek,

You can find some recommendations for EQ/DE settings in the datasheet (p. 11-12) and the DS64BR111EVK User's Guide (p. 8), though our measurements are taken with twin-ax cable and not a SAS/SATA cable. If you have a Vector Network Analyzer (VNA) available, you should be able to measure the loss in dB with the S-parameters from the cables you are using.

Thanks,

Michael

Hi Michael,

you were asking for estimation of cable loss. The manufacturer lists:

Attenuation: 10 dB/9 m Maximum @ 1.25 GHz - so lets assume ~12dB for 4m and 3GHz.

What would be the recommendation?

Thanks,

Jacek

Hi Jacek,

Recovering 12 dB of loss should not be an issue for the DS64BR111. On the channel direction that is receiving the -12 dB of loss, EQ = 0x03 or 0x07 may work well (we have noticed that the eye quality typically looks better with slightly less EQ gain than the advertised dB boost at 3.2 GHz in the datasheet). On the channel direction that is transmitting across the cable, I think de-emphasis of -3.5 dB should be sufficient.

These are recommended starting points, and we recommend that you err on the side of less gain than more when inserting the redriver in the data path. We expect that the ASICs on either side of the redriver have additional signal conditioning mechanisms, and if the redriver over-equalizes the signal, it can sometimes present more harm than good for the endpoint.

As an additional resource, please check out Webench Interface Designer (also can be referenced on the DS64BR111 landing page), where you can simulate with a variable amount of loss in dB between our redriver and the endpoint device. The simulation model uses our IBIS-AMI model to provide an expectation of part performance before implementing the design physically on the bench.

Thanks,

Michael

Hi Micheal,

more questions:
- SN75LVCP422 - previous chip we used didn't mention any ESD warnings claiming the level of +/-8kV -this chip has listed >5kV with warning of ESD sensitive device. Did you record any instances of pines being zapped?
- Do you have a recommended layout design you can share? in Eval kid it is not listed.

Thanks,
Jacek

Hi Jacek,

The only information I have to go from is on the datasheet. This ESD value of 5 kV means that, at the least, the device can survive a zap of 5 kV for all pins. I am not sure how much greater we can survive above 5 kV.

Regarding recommended layout design, I suggest you take a look at the DS100BR111 datasheet, Section 11. This device is of an identical function and footprint as the DS64BR111 (it is rated for a higher data rate), and it should be a good start for how to layout the IC.

Thanks,

Michael

Hi Michael,

following up on your response reg. the cable length:

I noticed within the device pin description VOD_SEL pin has a restrictive:

>>Note: DS64BR111 OUTA is limited to 700mV in pin mode, see Table 4 for additional information<<. Does it mean it is note suitable for the "long" cable application when I would prefer to use the ENSMB = 0 (PIN MODE) for simplicity of application?

Thanks,

Jacek 

Hi Jacek,

Good observation. While it is usually preferred to have a higher VOD to open the vertical eye as much as possible, we have seen success with lower VOD on the output of the redriver, since the endpoint ASIC/FPGA/CPU will have signal conditioning CTLE, DFE, and VGA characteristics of its own to compensate for the cable loss.

For your application, since you are dealing with -12 dB @ 4 GHz, I don't think this 700 mVpp on OUTA should be a significant issue to cause us to advise against using the DS64BR111 in pin mode. However, I would try to give yourself the most flexibility in terms of driving a signal onto the cable when you implement your design.

I assume that one channel will be driving signal out onto the cable, while another channel will be receiving an input from the cable and then redriving to an on-board ASIC. Design the system such that the A-channel's output drives the minimum loss distance, i.e. the trace from redriver to ASIC. Therefore, you will not be limited by a minimum VOD on the B-channel side that will then be driving signal out onto the cable.

Thanks,

Michael

Hi Michael,

We will have a need to implement a solution for sending data over to 4 HD through the same cable. I see TI offers a chip ds64br401 which is similar to the one we discussed just before. I see the differences though power supply is 2.5V not 3.3V. - are there any other differences?

Fundamental question is if I need to used only one bidirectional channel or two is it the others not used would "harm" the functionality of those being used? Is there a way to disable those not being used?

Thanks,

Jacek

Hi Jacek,

The DS64BR401 operates with a previous generation of redriver design compared to the DS64BR111, so programming the device would also require a little bit of study. Also, the DS64BR401 has a rate pin that controls the de-emphasis pulse width, which is a feature that the DS64BR111 (and other more recent products, such as the DS80PCI402/800 and DS125BR401A) do not use. I would check back on the datasheet to ensure that everything is set as you expect.

To answer your fundamental question, if you do not use a particular channel of the redriver, the redriver will mute the output of the unused channel. This is true for either the DS64BR401 or the DS64BR111 and is set by the electrical IDLE detect threshold. If the electrical IDLE threshold is not surpassed, the unused channel outputs will stay muted and will not interfere with functionality of the active channels.

Thanks,

Michael

Thanks Michael,

Few new suggestions. DS80PCI402/800 or the other alternative DS125BR401A came back to 2.5/3.3V power supply whereas DS64BR401 has bee left at 2.5V only. Why is that - is it 2.%V was not completely successful? Or are there any other reasons like signal compatibility with existing signal conditioning?
Do you offer additional apps notes for those three chips?

Jacek

Hi Jacek,

As previously mentioned, the DS64BR401 is a previous generation, so there was only one supply (2.5 V). In later designs like the DS80PCI402/800 and DS125BR401A, we integrated an internal LDO and created a 3.3 V mode and 2.5 V mode so that users have the flexibility of providing either 3.3 V to the device or 2.5 V. If 3.3 V is supplied to these newer devices, the redriver will use the LDO to regulate the 3.3 V input down to an internal 2.5 V. Alternatively, you can supply 2.5 V to VDD directly and bypass the LDO. In the DS64BR401, the only option is to supply 2.5 V to the device. There is no internal LDO.

This difference in voltage supplies does not affect the ability to perform signal conditioning or be compatible with SATA/SAS/PCIe signals.

Any literature for these three chips that we have available are provided in the "Technical Documents" tab for their respective landing pages.

Thanks,

Michael

Thanks Michael,

sounds like your recommendation is DS125BR401A rather than the one I originally started with. It has the same 3.3V supply voltage option -40 - +85degC operating temp range [unlike DS64BR401 from -10degC]. So the last question is does it represent the same driving strength capabilities as DS64BR111 in terms of cable length? Does it have the same settings required as we discussed before?

Thanks,

Jacek 

Hi Jacek,

Yes, I agree. From a support standpoint, for new designs at 6 Gbps (SATA 3.0), I would go with the DS125BR401. Here's an explanation of the difference between the DS125BR401 v. DS125BR401A so hopefully it is clearer:

1. DS125BR401: It is basically a 4-lane (8-channel) version of the DS64BR111. The digital controls are virtually the same as the DS64BR111, and the way that the signal detect, OOB support, and EQ/DEM/VOD configuration settings work are comparable.

2. DS125BR401A: The DS125BR401A is a newer device primarily used to benefit applications at 12G (SAS-3). At SAS-3, Link-Training between ASICs is a requirement, and we developed an Advanced Linear channel design for the A-bank channels (Channels 4-7) to support this. Meanwhile, the B-bank channels (Channels 0-3) remain the same design as the DS125BR401. Because the A-bank channels are a newer design, there is less CTLE boost and no de-emphasis controls available for these channels, but the output of these channels track the input waveform much more linearly than the B-bank design in order to capture critical pre-cursor and post-cursor information used in the Link-Training sequence.

Since you are designing for operation at 6 Gbps and not 12 Gbps, I do not anticipate a critical need to obtain an Advanced Linear device, since you will not need to support Link-Training. Therefore, I think for the sake of continuity between what you already know with the DS64BR111, the DS125BR401 may be a better fit here.

Michael