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DP83867IS Strap option

xiao peng ma
Intellectual 640 points
Other Parts Discussed in Thread: DP83867IS

I have read the DP83867IS  datasheet.

There are some bits in the STRAP_STS1 and STRAP_STS2 Register without corresponding Strap pins.

IE.STRAP_LINK_DOWNSHIFT_EN.STRAP_RGMII_DIS..etc

How to configure these bits?

  • 0
    TI__Mastermind 19780 points

    Hi Xiao,

    Strap options are usually configurable through MDIO registers even if the option isn't available on the pins.  The most common exception to this is the PHY address which can not be configured through MDIO access.

    The link downshift feature is referred to as speed optimization in the DS.  Speed optimization can be configured in the CFG2 register address 0x0014

    RGMII enable/disable is found in the RGMIICTL register address 0x0032

    Best Regards,

  • 0 in reply to Rob Rodrigues
    Intellectual 640 points

    Thanks.

    There is another question.

    In the RGMIICTL register,the default value of the RGMII_EN bit  is 1.

    It means that the default MAC interface is RGMII.

    Though  RGMII Clock Skew RX and RGMII Clock Skew TX can be set by Strap option,the default value of the RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY are both 0.

    RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY  must be set through MDIO if I want use RGMII Clock Skew value after POR?