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[ DS90UB914A ] LOCK Detect Condition and General Receiver Status Check

Kenichiro
Mastermind 9165 points

[ DS90UB914A ] LOCK Detect Condition and General Receiver Status Check

Hi,

Can anyone help me to figure out the answer of following questions?

Q1:

Can you please let me know exact LOCK detection condition where DS90UB914A to determine LOCK or UNLOCK to incoming signal?

 

Q2:

In order to check the incoming signal and deserializer status with register, I have suggested following registers to be checked.

0x1A[7:0], Parity Errors: Number of parity errors in the Forward channel during normal operation.

0x1B[7:0], Parity Errors[7:0]: Number of parity errors in the Forward channel during normal operation.

0x1C[2]: Parity Error: Parity Error detected.(1: Parity Errors detected., 0: No Parity Errors.)

0x1C[1]: Signal Detect: 1: Serial input detected, 0: Serial input not detected.)

0x1C[0]: De-Serializer CDR, PLL's clock to recovered clock frequency. (1: De-Serializer locked to recovered clock., 0: De-Serializer not locked.)

Please let me know, if I miss some other valuable registers.

Q3:

PASS pin will work not only for BIST mode, but also for normal operation. Correct?

Thanks,

Ken

  • 0
    Mastermind 9165 points
    Hi,

    Can anyone help me to support these queries from customer??

    Thanks,
    Ken
  • 0 in reply to Kenichiro
    TI__Expert 5210 points
    Hello Ken,

    1. LOCK is determined by the PLL. If the PLL can track, i.e. "lock" to the incoming data stream coming from the serializer then the Ser/Des system will work and the the LOCK pin will go high. If the signal integrity has either a.) too much jitter or b.) too small of a voltage swing (Vswing) then the PLL on the 914A won't be able to the data stream coming from the 913A. Many things as you know can influence signal integrity such as cable loss, PCLK jitter, etc. If the Vswing is too small, then the adaptive equalizer on the 914A will boost the signal margin so that the internal PLL has a better chance to LOCK to the 913A data stream.

    2. Yes, these are good registers to reference to check LOCK status and also check for forward channel errors on the data stream.

    3. That is correct. PASS pin will go low in the presence of forward channel errors for both normal operation mode and BIST mode.

    -Sean
  • 0 in reply to Sean Thornton1
    Mastermind 9165 points
    Hi Sean,

    Thank you for your reply!
    With regards to Q1, do you have more detail numbers that DS90UB914A to determine the out of lock condition? For example, phase detector detect time deference between incoming signal and VCO within certain period, VCO goes away xxxppm from its center freq. exc...

    Thanks,
    Ken