DS80PCI402SQ trying to get oputput

Hi Robert,

Just applying power should be enough to see data at the A outputs (since there is signal present on the input side).

For SMBus access what is the device address?  DEMB[1:0] and EQB[1:0] should be pulled to a H/L level to establish ADR[3:0].

You should be able to read from  register 0x06 = 10'h to know you are reading from the device correctly.

Other questions:

Is there a valid receiver load connected to the DS80PCI402 outputs?

Is the DS80PCI402 AC coupled to the input and output sides of the system?

Regards,

Lee

Yes, the 4 addr pins are pulled low. We can read and write all I2C registers. Inputs and outputs are AC coupled. Output behavior is no different regardless of receiver load present or not. And that goes to the issue of trying to supersede the RX Detect functionality - in the near term I want to be able to force outputs on or off. I think the register settings I provide should do this.

Thanks,

Rob

Rob,

There are a couple things to try.

Force input termination "on" -  Easiest way is with pins. Pull RXDET pin Low.

Using registers is a bit more work, but should force the outputs "on" no matter what the input conditions.

Write Register 0x08 = 10'h    //* Idle/mute control by register - not signal detect pin threshold

Write Register 0x2B = 20'h    //* Ensure CHA-0 on

Write Register 0x32 = 20'h    //* Ensure CHA-1 on

Write Register 0x39 = 20'h    //* Ensure CHA-2 on

Write Register 0x40 = 20'h    //* Ensure CHA-3 on

Also,

Power device up with RXDET floating and check the following registers

0x2E, 0x35, 0x3C, and 0x43 to see what the status of RXDET and RATE_DET is for each of the A-side channels.

Regards,

Lee

This solved out problem with getting output.

However we are now having a problem between channels. We are getting different RATE_DET even though the inputs are all the same properties. For registers 0x2E, 0x35, 0x3C, and 0x42 we get 0x00, 0x20, 0x60. I would expect 0x00 for all of them. And the output is different. CHA_0, CHA_1 output amplitude is much larger than that of CHA_2 and CHA_3 amplitude. 

Why would they be different. Is there a way to force them to be the same?

Hi Robert,

Ok - I'm glad you are gettting output now. Please send in a list of all the register values 0x00 - 0x61

Regards,

Lee

This is what I have for now. It will take some work to get the others.

DS80_PWDN_CH ; 0x01; ------; 0x0000000f;
DS80_PRSNT_LPBK ; 0x02; ------; 0x00000031;
DS80_SLV_RG_CTL ; 0x03; ------; 0x00000018;
DS80_DIG_RST_CTL ; 0x07; ------; 0x00000001;
DS80_OVR_PIN_CTL ; 0x08; ------; 0x00000010;
DS80_Sig_DET_MON ; 0x0A; ------; 0x0000000f;
DS80_Sig_DET_STAT_CTRL ; 0x28; ------; 0x00000000;
DS80_CHA0_IDLE_RXDET ; 0x2B; ------; 0x0000002c;
DS80_CHA0_EQ ; 0x2C; ------; 0x0000003f;
DS80_CHA0_VOD ; 0x2D; ------; 0x000000e8;
DS80_CHA0_DEM ; 0x2E; ------; 0x00000000;
DS80_CHA0_IDLE_TH ; 0x2F; ------; 0x00000000;
DS80_CHA1_IDLE_RXDET ; 0x32; ------; 0x0000002c;
DS80_CHA1_EQ ; 0x33; ------; 0x0000003f;
DS80_CHA1_VOD ; 0x34; ------; 0x000000e8;
DS80_CHA1_DEM ; 0x35; ------; 0x00000020;
DS80_CHA1_IDLE_TH ; 0x36; ------; 0x00000000;
DS80_CHA2_IDLE_RXDET ; 0x39; ------; 0x0000002c;
DS80_CHA2_EQ ; 0x3A; ------; 0x0000003f;
DS80_CHA2_VOD ; 0x3B; ------; 0x000000e8;
DS80_CHA2_DEM ; 0x3C; ------; 0x00000060;
DS80_CHA2_IDLE_TH ; 0x3D; ------; 0x00000000;
DS80_CHA3_IDLE_RXDET ; 0x40; ------; 0x0000002c;
DS80_CHA3_EQ ; 0x41; ------; 0x0000003f;
DS80_CHA3_VOD ; 0x42; ------; 0x000000e8;
DS80_CHA3_DEM ; 0x43; ------; 0x00000060;
DS80_CHA3_IDLE_TH ; 0x44; ------; 0x00000000;

Hi Robert,

I think we should be able to work with these settings for now. I looked through the thread and noted that we might have suggested the RXDET pin value incorrectly in order to force the output to be on. To force the input termination "on" so that the inputs are connected to VDD via 50-ohm termination, RXDET should be pulled high via 1 kOhm to VDD instead of pulled low. What is the RXDET value when you read back these register values?

Also, I noticed that the EQ value is high (0x3F). This should not affect your ability to activate channel, but it may affect the negotiated data rate, as an over-equalized signal through the repeater can lead to eye closure at higher data rates, such as PCIe Gen-3.

Thanks,

Michael

I got access to the higher register contents and it appears to all be the default values listed in the data sheet.

The RXDET pin is floated.

The RXDET register value is 11b (reg = 0x2c).

What seems to be my biggest problem right now is the "Observation bit for RATE_DET" in the DEM registers. Which it detects has a huge impact on the signal output. What I want, what would be correct (vis a vis rate, not GEN as this is not PCI), and what produces better signal at the receive end is "GEN1 - 2.5G".

But for some reason I don't understand, it reports GEN3 and infrequently GEN2. This seems to be random as the same signal is present on all lanes yet some detect as GEN1 and others as GEN3. And this is also random in that a given lane seems to detect one or the other randomly.

This wouldn't be so bad except for the fact I don't see a way to force it to be one or the other. If I could just force GEN1, that would be ok.

What is the detection calculus that determines GEN1 or GEN3?

Also, the VOD setting and RATE_SEL does not seem to make any difference.

Thanks,

Robert Miller

Hi Robert,

In the DS80PCI402, there is a mechanism that determines the rate passing by according to the data rate detected by the internal rate-detect circuit (PCIe Gen-1 (2.5G) / Gen-2 (5G) / Gen-3 (8G)). If you use a non-PCIe standard data rate, this RATE detect may potentially switch between the "generation" it detects, depending on if you are near a threshold between when the repeater picks one Gen over another.

However, I think you can circumvent this issue by overriding the RATE pin and forcing the rate to be Gen 1/2. By overriding the RATE pin, this means that you are forcing the repeater's output driver to operate in limiting mode, i.e. the output VOD and de-emphasis are determined by a limiting driver. Forcing the device to be Gen 3 means that you are forcing the repeater's output driver to operate in non-limiting (or linear) mode, i.e. the output VOD and de-emphasis are more linearly amplified through a linear driver path.

The logic behind the nomenclature is that Gen 1/2 are better suited when precursor/postcursor link-training is not part of the link-up protocol. Since PCIe Gen-3 requires link-training with varying precursor/postcursor presets P0-P10, a non-limiting driver is preferred in this scenario.

To override RATE for CHA_0 to CHA_3, implement the following:

Reg 0x08[2] = 1 //Block RATE pin control and enable RATE_SEL to take affect for each channel
Reg 0x2D[6] = 1 //Force Gen 1/2 for CHA_0
Reg 0x34[6] = 1 //Force Gen 1/2 for CHA_1
Reg 0x3B[6] = 1 //Force Gen 1/2 for CHA_2
Reg 0x42[6] = 1 //Force Gen 1/2 for CHA_3

Meanwhile, since you are forcing the RXDET bits to be 11'b, (for example, in Reg 0x2B), please ensure that Reg 0x08[3] = 1 in order to block RXDET pin control.

If you don't mind sharing a schematic of your implementation, that could be helpful for us to do some further debugging as well.

Thanks,

Michael

Reg 0x08[2] = 1 //Block RATE pin control and enable RATE_SEL to take affect for each channel

This seems to have fixed that issue. It still reports GEN3 randomly, but at least the output is now consistent across all lanes. Our data rate is 2.5G, so there should not be any ambiguity on detection.

However, VOD and DEM do not appear to have any effect on the output. Is there some other bit required to enable those parameters?

Thanks,
Robert Miller

I have VOD and DEM working now too. I just turned on all the override bits in reg 0x08. Now I can control everything I think I should be able to. I think now I just need to play with the parameters to get it tuned in.

The slave control bit was one of the first ones we figured out a while ago. So that must have been a typo then.

Thanks,
Robert Miller

Hi Robert,

Sounds good. Good luck, and if you run into any further issues with settings, please feel free to reach out again.

Michael