TLK10232 XAUI errors

Hi Yuli,

TLK10232 does not have an active register to disable invalid data on XAUI output when the link is down. There are some "indirect" solutions but it means "hardware solution" (please refer to TLK10232EVM users guide to take a look in a possible solution).

Best Regards,

Luis Omar Morán Serna

High Speed Interface

SWAT Team

Hi, Luis.
I've got errors on RX lanes, not transmit.
I even disconnected TX to ensure that there is no influence on FPGA, but still getting errors.
Why there is dependence TX direction on HS RX ?

Regards,
Yuli

Hello Yuli,

Could you clarify if you are getting errors only when you disconnect (unplug) the optical fiber cable? Or even when the cable is connected?

Regards,
Luis

Hi, Luis.

It is happening when plug or unplug fiber only.

When cable is connected there are no errors.

I cannot explain why it affect XAUI receive and then sent to line.

BR,

Yuli

Yuli,

Basically the data is accepted on the low speed side (XAUI) SERDES pins (IN*P/N), transverses the transmit data path up to the HS SERDES, then is sent out through the HSTX*P/N pins (backawards if the data is from the high speed side).

To prevent invalid data on the high speed ouputs, user could use the HS_LOS indicator or the actual LOS pin as indicators that the received data should not be considered valid.  You could also configure the internal XAUI data switch (DSR) to use a different data source (like the XAUI input of the same channel or another input port's data) when a local fault is detected on the HSRX input.

Best Regards,
Luis

Hi, Luis.

I understand that on connection errors can appear .
I would like to know how to avoid errors on transmit path when I get errors on receive path.

I see errors on XAUI input (LS TX path) when disconnecting or connecting the HS RX.
I do not understand why TX path is affected from RX path. My understanding is that they should be completely separate from one another.

I even physically disconnected XAUI TX (RX path) from FPGA to ensure that the errors are not caused from internal FPGA code.

BR
Yuli

Hello Yuli,

In these transceivers the RX and TX blocks shares circuitry. This device is able to correct a burst of errors up to 11 bits (Forward Error Correction), although if the user unplug the optical fiber, this FEC will not able to correct a large amount of errors. In this kind of scenario, user could use the LOS indicator and then use the data switch to send out a valid data (pattern such as PRBS, etc.).

I hope this helps.

Best Regards,

Luis Omar Morán Serna

High Speed Interface

SWAT Team

Hi, Luis.
That means any event on RX will impact TX?
In this case , is any possibility to transmit IDLEs or some legal data to opposite side?
And then, switch to LS side and proceed to regular data?
And what should I do in case of only half of PHY is in use?

Regards,
Yuli

Hi Yuli,

Yes, any event on RX will impact TX. So, in this case user could enable the PRBS generator to send valid data when the cable is disconnected and when the cable is connected (monitoring LOS indicators) switch to the valid data.

If you are going to use only 1 channel of the TLK10232, I wil suggest the TLK10031 is the single channel version of TLK10232.

Best Regards,

Luis Omar Morán Serna

High Speed Interface

SWAT Team

Hi, Luis.
I will try to explain situation.
We have two units connected to CWDM system via long fiber.
Latency is about 3 ms.
System is transferring states on both sides transparently.
At any attempt to get stable link we are getting errors on XAUI (regs 0x11-0x14) (10G link side)
The delayed errors just travelling over the system.
The working solution is to place switch on any side of link.
Regular Ethernet switch does NOT transferring RX errors to TX, what your PHY does.
This is the difference.
Can you suggest some?
You previous suggestion to use PRBS will not solve the problem, because link will be down in that case.
And attempt to return to regular transfer will cause errors on TX again.

Regards,
Yuli