Screen image shifted for HDMI to LVDS

Hi Vo,

Can you share your schematic as well as a picture of what a correct screen image looks like? We'll try to debug based on your current design and your expectation of what a correct output should look like.

Also, what is your pixel clock frequency for this design?

Thanks,

Michael

Hi Michael,

The pixel clock is about 74.16MHz.

Please see schematic, correct screen and LCD datasheet for your reference in the zipped file.

Thank you very much,

Vo

Sharp 17.0 SXGA LQ170E1LW22.zip

Hi Vo,

I looked at the schematic and the LCD panel datasheets this morning. The schematic that you show for the LCD control console looks reasonable to me, and all the settings look correct when interfacing the TFP401A to DS90C387A in a dual-link application. 

I also double-checked the LVDS interface block diagram on the LCD panel datasheet and verified that the THC63LVD823B in this application serves an equivalent function to the DS90C387A:

One thing that came as a surprise to me is the timing characteristics required by the Sharp display (Section 7-1). It shows that the expected pixel clock is 54 MHz, which differs from the 74.16 MHz you are providing. Is this correct? If so, I suspect that the TFT panel's PLL is not locking correctly to the expected clock range (50-58 MHz).

Can you comment on the failure rate of the LCD? Does this issue happen all the time, or on only a small percentage of display panels?

Thanks,

Michael

Hello Michael,

Thank you very much for your reply and review the schematic.I think your suggestion of looking into the pixel clock is a really good one.

I tried another  similar TFT panel ( different manufacturer), but with max pixel clock up to 70MHz, The command bar is not shifted down anymore,

but the text " Windows Embedded Compact 2013" are still off center. Please see screen image and timing for the other TFT panel.

Do you think reducing the pixel clock on the HDMI input to meet the spec for the Sharp display is the right direction ?

We are still under development with Sharp Display, but the display works fine with off the shelf LCD controller.

Thanks,

VoG170EG01V1.zip

Hi Vo,

That is strange that it works with the different TFT panel. I find the timing specification for this new module strange as well. It appears that this Au Optronics module specifies that the interface timing characteristics in the table are actually just the "output timing of SN75LVDS82DGG or equivalent." However, when comparing the timing characteristics in Section 6.4.1 with that of the SN75LVDS82DGG, it doesn't match up. The SN75LVDS82DGG is a Flat-Link Receiver rated for 31-68 MHz pixel clock, so there is no assurance from the datasheet that the device works as expected above 68 MHz.

If the device is off-center horizontally or shifted vertically, I think something is off with the PLL such that the HSYNC and VSYNC signals are appearing in the wrong place and therefore start a new line or divide up each frame in the wrong place. If possible, try lowering the pixel clock to 54 MHz and see if this makes a difference.

I have a few thoughts and questions:

The off-the-shelf LCD controller you mentioned...is there a way to get a scope and measure the Pixel Clock at its output? I'm curious to see what operating frequency is coming out of the LCD controller that is currently driving the display correctly.

Thanks,

Michael

Hi Vo,

Glad to hear things are working. Best wishes with the rest of your design.

Michael