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SN65DSI84 MIPI Integration

Steffen Sutton
Prodigy 30 points
Other Parts Discussed in Thread: SN65DSI84

Hello there,

I apologize in advance if this question is rather basic, but I am not 100% clear on what the MIPI standard encompasses.

Does the data transmission protocol for the MIPI DSI input need to be defined for the SN65DSI84 integration?

Or since this product is supposed to be industry compliant, will the SN65DSI84 decode the video stream and provide LVDS output as defined from the datasheet without further configuration?

Essentially, will this IC act as drop-in to bypass the MIPI interface?

Any help would be much appreciated.

Thank you ,

Steffen S.

  • 0
    TI__Mastermind 18655 points

    Hello Steffen,

    The video transfer is done on a line-by-line basis. The SN65DSI8x will match the line time (Sync-to-Sync time) between the input and the output.
    The LVDS output timing is generated based on the CSR values programmed in the corresponding video parameter fields. The following values need to be programmed tocreate the timing for the LVDS panel; HSync pulse width, HSync Back Porch duration, and VSync pulse width.

    It is also important to maintain the data rate so as not to underflow or overflow the internal buffer. The SN65DSI8x supports a programmable delay value to help maintain the data rate and the availability of data in internal buffers. The delay value, also referred as “sync delay”, is used to delay the outgoing data, up to 0xFF number of pixels, by programming the corresponding register field. The sync delay value can be calculated based on the DSI input parameters and the
    LVDS output requirements. It is important to program the sync delay value to a properly calculated value for correct operation of the device.

    Regards,
    Joel