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TPS65982: Is the SPI bus tristated when hreset is asserted?

Michael Lew
Prodigy 20 points
Other Parts Discussed in Thread: TPS65982

I was wondering what the state of the SPI bus is when hreset is asserted and held. Is it tristated or somehow disconnected while in reset (not interested in the POR state)? 

Thanks! 

  • 0
    TI__Mastermind 30310 points

    Michael,

    HRESET Low = POR before any digital code executes.

    As long as HRESET continues to be low, BOOT code will not execute and there will be no activity on the SPI pins generated by the TPS65982.

    If you refer to Figure 61 in the TPS65982 datasheet, the circuit is merely a comparator input and a CMOS output with SPI_OE (output enable) pulled low.

    The word tri-state would not apply to any pin that requires a pull-up resistor (SPI_SSZ, SPI_MISO), since they must be held high.

    And since a clear distinction is made between "Digital Input" (SPI pins) and "Hi-Z" (most GPIOs) for POR State in the Pin Function table, I would suggest that SPI_CLK and SPI_MOSI are not truly Hi-Z and are therefore not tri-state capable.